Senior Analog MS IC Layout Engineer - France

microTECH Global Ltd; France; Sur place; EUR 60 000 - 90 000; Plein temps

Résumé du poste

A dynamic and motivated Senior Analog MS IC Layout Engineer is sought to join a leading company in France. The role focuses on the physical implementation and verification of analog and mixed-signal ICs, requiring 6 years of experience and expertise in Cadence tools. Candidates should have a proven track record in IC development from specification to production, along with excellent analytical and team collaboration skills.

Qualifications

• Minimum 6 years experience in IC development.
• Participated in IC product from specs to mass production.
• Hands-on experience in mask design for analog/mixed-signal functions.

Responsabilités

• Define ASIC floorplan, input/output pin placement.
• Perform physical verification (DRC, LVS, ERC, EM).
• Generate post-layout netlist with parasitic extraction.

Connaissances

Analytical skills

Problem-solving skills

Team player

Attention to detail

Outils

Cadence analog layout flow

Description du poste

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Senior Analog MS IC Layout Engineer - France, france

Client: microTECH Global Ltd

Location: France

Job Category: Other

EU work permit required: Yes

Job Reference: b28c1e55e5ae

Job Views: 3

Posted: 24.06.2025

Expiry Date: 08.08.2025

Job Description:

Job function:
Our client's Layout Team is seeking a dynamic and highly motivated Layout Engineer to work on physical implementation and verification of analog and mixed-signal ASIC functions to deliver state-of-the-art Integrated Circuit (IC) in deep submicron CMOS technology.

Work description:

• In close collaboration with analog, mixed-signal and digital designers, define the ASIC floorplan and its sub-blocks, input/output pin placement and top-level assembly
• Full-custom physical implementation of high speed and high-performance analog, mixed-signal blocks including integration of digital macros.
• Optimize the layout to meet circuit area and performance requirements
• Optimize the layout with respect to voltage drop, matching, speed and coupling.
• Perform sign-off physical verification of sub-blocks and/or top chip meeting all manufacturing requirements (DRC, LVS, ERC, EM)
• Generate post-layout netlist with parasite extraction tools.
• Work in team to design a state-of-the-art integrated circuit.
• Prepare / participate in layout reviews.
• Write the documentation respecting the quality policy.
• Respect and execute the development steps in accordance with the company's development methodology.

Qualification and Experience:

• You have at least 6 years of experience in the integrated circuit development with successful tape-out track record.
• You have participated in the development of an IC product from specifications to mass production
• Hands-on experience in mask design for analog and/or mixed signal functions with strong matching, low parasitic, low coupling requirements.
• Solid knowledge of Cadence analog layout flow including mask checks (LVS, DRC, ERC, EM)
• You demonstrate excellent analytical and problem-solving skills
• You are a team player with a critical attitude and sense of initiative
• You are a professional who can deliver high-quality work on tight schedules
• Fluent in English