Senior Analog & Mixed-Signal Design & Verification Lead

Chipright; France; Sur place; EUR 90 000 - 140 000; Plein temps

Résumé du poste

Chipright in France is seeking a Senior Analog & Mixed Signal Design/Verification Engineer with at least ten years in the semiconductor industry to lead transistor-level design. You will develop and characterize analog/mixed-signal blocks (ADCs, DACs, PLLs) and contribute to IP or IC products from specs to mass production, collaborating with a skilled team.

Candidates should master Cadence or Mentor flows and be comfortable Verilog-A or MATLAB modeling, with strong analytical and leadership

Qualifications

• Minimum ten years of experience in the semiconductor industry as an Analog & Mixed Signal Designer.
• Experience in the development of an IP or IC product from specifications to mass production.
• Experience in design and characterization of analog and mixed-signal functions or RF blocks such as ADCs, DACs, PLLs, Bandgap references.
• Knowledge in semiconductor physics, biasing and reference circuits, switched-cap and continuous-time circuits, feedback systems and compensation techniques, signal processing.
• Has excellent analytical and problem-solving skills.
• Experience of taking high-level specifications and turning them into transistor-level design is required.
• Experience using Cadence or Mentor analog design flow is necessary.
• Familiarity with behavioral modeling in Verilog-A or MATLAB is necessary.
• You have the ability to manage people so they give the best of themselves.
• Experience working as a team player with a critical attitude and sense of initiative

Connaissances

Analog Design

Mixed-Signal Design

RF Blocks

Transistor-Level Design

Analytical Skills

Team Leadership

Verilog-A

MATLAB

Outils

Cadence

Mentor Graphics

Description du poste

Chipright in France is seeking a Senior Analog & Mixed Signal Design/Verification Engineer with at least ten years in the semiconductor industry to lead transistor-level design. You will develop and characterize analog/mixed-signal blocks (ADCs, DACs, PLLs) and contribute to IP or IC products from specs to mass production, collaborating with a skilled team.

Candidates should master Cadence or Mentor flows and be comfortable Verilog-A or MATLAB modeling, with strong analytical and leadership