Principal Engineer - CAD Physical Verification

Microchip Technology Inc.; Rousset-Serre-Ponçon; Sur place; EUR 73 000 - 160 000; Plein temps

Résumé du poste

A leading technology firm in Provence-Alpes-Côte d'Azur is seeking an experienced Verification Engineer to develop and support physical verification. The role requires strong knowledge of Siemens Calibre and Cadence Pegasus, with 8+ years of relevant experience. This position offers competitive compensation including base pay, bonuses, and robust health benefits starting day one.

Prestations

Competitive salary

Health benefits from day one

Retirement savings plans

Restricted stock units

Quarterly bonuses

Qualifications

• 8+ years developing and supporting physical verification activities.
• Fluent with SVRF and TVF.
• Strong knowledge of Design for Manufacturing solutions.

Responsabilités

• Develop physical verification regression test cases.
• Support Layout/Design engineers with verification activities.
• Develop DRC rules and design for manufacturability checks.

Connaissances

Calibre DesignRev scripting

Debugging PV issues with RVE

Customization of Calibre Interactive

Knowledge of Tcl/Tk, Perl, Python

Solid knowledge of layout rules

Design for Manufacturing knowledge

Strong knowledge of Cadence Virtuoso

Excellent verbal and written communication

Outils

Siemens Calibre

Cadence Pegasus

Synopsys Hercules

Description du poste

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Job Description

The CAD group at Microchip offers global support for multiple technology nodes and tools used in product development providing innovative solutions for the design community. The candidate will focus on flow development and support for back end physical verification. If you have a solid software background and are interested in supporting semiconductor chip design, this maybe the job for you.

Expertise using Siemens Calibre and/or Cadence Pegasus DRC, LVS and PERC tools is paramount. Candidate should not only know how to run the tools and debug results, but also have strengths in developing the verification run decks and in automating flow/procedures.

An overall strong understanding in both the digital and analog sides of design is important to be effective, since development and support work will span a variety of design styles. Additionally, both circuit/electrical and layout/physical knowledge is important.

Responsibilities

• Develop physical verification regression test cases to QA physical verification decks
• Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules
• Utilize Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc.
• Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks
• Develop rule decks as needed to support flow
• Verify and enhance foundry rule decks
• Support remote sites worldwide with layout verification activities
• Support debug of physical verification issues
• Work as a member of team to develop flows to improve quality and reliability of devices

The Tasks This Candidate Will Be Assigned Depends On Their Experience. There Are Several Areas In Which We Are Shorthanded. Potential Task Assignments Would Include

• Building of regression test cases for several PDKs of various process technologies
• Supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc.
• Calibre/Pegasus PERC – several PDKs still require PERC setup.

Requirements/Qualifications

• 8+ years developing and supporting physical verification activities
• In depth knowledge of Calibre DesignRev scripting
• Fluent with SVRF and TVF
• Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer
• Familiar with customizing Calibre Interactive Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools
• Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules
• Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs
• Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool
• Strong knowledge of Cadence Virtuoso and/or CalibreDRV
• Prefer Extraction, Reliability and Dynamic Noise related knowledge
• Excellent verbal and written communication and interpersonal skills

Travel Time

0% - 25%

Pay Range

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature.

The annual base salary range for this position is $86,000 - $186,000.

• Range is dependent on numerous factors including job location, skills and experience.

Microchip Technology Inc. is an equal opportunity employer and welcomes applications from diverse candidates. In accordance with applicable laws, accommodation will be provided in all parts of the hiring process. If you require accommodation, please contact us at [e-mail].