HW/SW Co-Design Research Engineer – Memory Systems & GEM5

European Tech Recruit; Paris; On-site; EUR 65,000 - 100,000; Full time

Job summary

A HW/SW Co-Design Research Engineer is sought in Paris, France to join an advanced R&D team working on hardware/software co-design for memory management optimisation in many-core systems.

The role emphasizes GEM5-based simulation, OS-level software, and performance analysis, with publication-ready research and documentation.

Candidates should have hands-on GEM5, strong C/C++, Linux experience, and a PhD or equivalent R&D background; publication record preferred.

Qualifications

• Hands-on experience with GEM5 benchmarking and simulation.
• Strong understanding of computer and memory architecture.
• Experience with Linux and systems programming.

Responsibilities

• Develop and simulate many-core architectures using GEM5, focusing on memory management.
• Prototype and evaluate memory atomic operations in distributed shared-memory systems.
• Investigate memory hierarchy, cache coherence and memory consistency behavior.
• Develop OS-level software to support IPC within the proposed memory architecture.
• Collaborate across HW/SW boundary to evaluate architectural choices.
• Design experiments and performance benchmarks.
• Analyse results and prepare publications and technical docs.

Skills

GEM5

C/C++

Memory hierarchy

OS memory management

Linux

Education

PhD

Tools

GEM5

Job description

HW/SW Co-Design Research Engineer – Memory Systems & GEM5

Location: Paris, France

Contract: Fixed-Term Contract (CDD)

We are looking for a Research Engineer / Systems Engineer to join an advanced R&D team in Paris working on hardware/software co-design for memory management optimisation in many-core systems.

The work sits at the intersection of computer architecture, operating systems and memory systems, with a strong focus on simulation, prototyping and research.

Responsibilities

• Develop and simulate many-core architectures using GEM5, with a particular focus on memory management
• Prototype and evaluate memory atomic operations in distributed shared-memory systems
• Investigate memory hierarchy, cache coherence and memory consistency behaviour
• Develop OS-level software to support inter-process communication (IPC) within the proposed memory architecture
• Work across the HW/SW boundary to evaluate architectural and software design choices
• Design experiments and performance benchmarks
• Analyse results, produce plots and identify optimisation opportunities
• Contribute to research publications and technical documentation

What We’re Looking For

• Previous hands-on experience with GEM5
• Strong understanding of computer and memory architecture
• Strong knowledge of how memory is managed by the operating system
• Detailed understanding of cache/memory coherence
• Knowledge of shared memory, memory consistency, virtual memory, NUMA and/or atomic operations
• Strong C and/or C++ programming skills
• Experience with Linux, operating systems, systems programming or kernel-level development
• Research or R&D experience in computer architecture, operating systems, HPC or related areas
• At least one published research paper as first author
• Comfortable designing experiments, analysing performance data and contributing to publications

Particularly Relevant Backgrounds

Candidates may come from areas such as Computer Architecture, Operating Systems, Memory Systems, HPC, Many-Core Architecture, HW/SW Co-Design, Systems Software or Architecture Simulation.

A PhD is highly relevant, although we are also interested in strong Research Engineers with equivalent industrial R&D experience and publications.

If your background includes GEM5, cache coherence, memory architecture and low-level C/C++ systems development, I’d be very interested in speaking with you.

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