FY27 Intern- AI-Driven Power Modeling for Evaluating Power Consumption in NoC IP Architectures - 6 months, Guyancourt

QUALCOMM, Inc.; Guyancourt; Sur place; EUR 6 700 - 13 000; Plein temps

Résumé du poste

Qualcomm France S.A.R.L. in Île-de-France, Guyancourt, offers a 6-month internship focused on power modeling for NoC architectures. You will build data prep workflows and ML-based power estimators to support early design decisions.

The project includes data preparation and ML modeling with deliverables such as a reusable dataset, AI models, and a prototype exploration tool. Proficiency in Python and English is required; Verilog/VHDL and ML frameworks are a plus.

Qualifications

• Final year master's student in Microelectronics, Computer Engineering or related field.
• Proficient in Python and Bash; familiarity with Verilog/VHDL and UVM is a plus.
• Experience with ML frameworks and strong English communication.

Responsabilités

• Assist data preparation for power characterization and NoC IP configurations.
• Develop ML-based power models and compare to reference results.
• Contribute to documentation and provide guidelines for NoC power-aware exploration.

Connaissances

Python

Bash

Verilog/VHDL

UVM

ML frameworks

English

Formation

Master's degree in Microelectronics / Computer Engineering

Description du poste

Company:

Qualcomm France S.A.R.L.

Job Area:

Interns Group, Interns Group > Interim Intern

General Summary:

ABSTRACT This internship investigates the impact of power consumption of Network-on-Chip (NoC) architectures and develops an AI/ML-based power modeling framework to estimate power consumption during early design stages. The objective is to enable fast and accurate evaluation of design choices while accounting for the effects of NoC IP Architectures, thereby facilitating power‑aware architectural optimization.

CONTEXT

QITC develops and deploys highly configurable custom-built NoC IPs, tools and methodologies so that worldwide SoC teams can assemble SoCs with the desired Power-Performance-Area (PPA) characteristics. The NoC IP Architectures/Topologies directly shape the power profile of the interconnect, yet their impact can today only be quantified late in the flow, through synthesis, gate‑level simulation and power analysis. Repeating this flow for every architectural option is prohibitively slow, which limits early power‑aware exploration.

MISSION & METHOD

The intern will build a two‑phase framework combining classical power characterization with machine‑learning‑based power modeling:

Phase 1: Data Preparation

• Design & scenario setup — Elaborate NoC IP Architectures/Topologies and define representative traffic.
• Power characterization — Run synthesis and simulations to capture activities profile and power.
• Dataset construction — Build a labelled dataset from the power characterization step (2)

Phase 2: ML based Modeling and Power Estimations

• AI power modeling — Train and compare AI Based models and assess accuracy against gate‑level references.
• Early design‑space exploration — Use the trained models to explore design in terms of power in seconds rather than hours.

EXPECTED DELIVERABLES

• An automated power characterization for NoC IPs
• A reusable power dataset and AI power models, with documented accuracy and speed‑up assessment.
• A prototype exploration tool and guidelines for power‑aware NoC architecture choices.

PROFILE & PRACTICAL INFORMATION

• Final year master’s degree in Microelectronics, Computer Engineering or a related field; interest in digital design, low power and machine learning.
• Scripting in Python and bash; notions of Verilog/VHDL, UVM, EDA flows and ML frameworks are a plus. Proficient in English.
• Duration: 6 months

References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Equal Opportunity

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e‑mail disability‑[e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.