Digital IC Design Engineer

TN France; Hérouville-Saint-Clair; Sur place; EUR 45 000 - 70 000; Plein temps

Résumé du poste

An established industry player is seeking a highly motivated Digital IC Design Engineer to join their dynamic design team. This role involves participating in the design of cutting-edge CMOS Transceiver ASICs for the Communications market. The ideal candidate will engage in architecture definition, RTL design, and verification of digital sub-blocks, collaborating closely with mixed-signal and digital IC design engineers. If you possess a strong background in digital electronics and signal processing, along with proficiency in hardware description languages, this is an exciting opportunity to contribute to innovative projects in a collaborative environment.

Qualifications

• 3+ years of experience in micro-architecture definition and RTL design.
• Proficiency in VHDL or Verilog and scripting languages.
• Experience with digital functions for Mixed-Signal ICs is a plus.

Responsabilités

• Define micro-architecture of digital sub-blocks and perform RTL design.
• Develop verification plans and write SDC constraints.
• Collaborate with the team to design state-of-the-art ASICs.

Connaissances

Digital Electronics

Signal Processing

RTL Design

Verilog/System-Verilog

Problem Solving

Analytical Skills

Team Collaboration

Fluency in English

Formation

MSc in Electrical Engineering

PhD in Electrical Engineering

Outils

TCL

Perl

Python

Cadence

Synopsys

Description du poste

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Client:

microTECH Global Ltd

Location:

Job Category:

-

EU work permit required:

Yes

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Job Reference:

0e67bed0a11b

Job Views:

4

Posted:

01.05.2025

Expiry Date:

15.06.2025

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Job Description:

Position: Digital IC Design Engineer
Location: Caen – France

About the role:

The company’s design team is seeking a dynamic and highly motivated Digital IC design engineer to participate in the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market.

The candidate will be involved in architecture definition, design, and verification of the ASIC digital sub-blocks in collaboration with mixed-signal and digital IC design engineers.

Responsibilities:

• Derive specifications and define the micro-architecture of the digital sub-blocks
• RTL design of the digital sub-blocks (Verilog/System-Verilog)
• Develop detailed verification plans based on circuit specifications
• Write SDC constraints
• Define block and top-level self-checking test benches, RTL, and gate-level netlists
• Participate in the evaluation of the fabricated ASIC in the measurement lab
• Collaborate with the team to successfully design a state-of-the-art ASIC
• Participate in design reviews
• Write documentation following company QA policies

Qualifications and Requirements:

• MSc or PhD in Electrical Engineering or equivalent with 3+ years of experience in micro-architecture definition, RTL design, and verification
• Strong background in digital electronics and signal processing
• Proficiency in hardware description languages (VHDL or Verilog) and scripting languages (TCL, Perl, Python)
• Solid knowledge of SystemVerilog
• UVM methodology experience is a plus
• Good analytical and problem-solving skills
• Experience with digital functions for Mixed-Signal ICs (A/D Converters, D/A Converters, RF transceivers) is a plus
• Experience with Cadence or Synopsys RTL design flow is a plus
• Team player with critical thinking and initiative
• Fluent in English (oral and written)