Analog IC Design Engineer - PLL

IC Resources; Paris; À distance; EUR 60 000 - 100 000; Plein temps

Résumé du poste

An innovative technology company is seeking a Senior Analog IC Design Engineer to lead cutting-edge developments in high-speed Phase Locked Loop design and integrated power management. This role offers a fantastic opportunity to work on energy-efficient interconnects and collaborate with cross-functional teams in a forward-thinking environment. Ideal candidates will have a strong background in CMOS analog design and experience with advanced nodes. The position may offer remote working options, making it a great fit for those seeking flexibility while contributing to groundbreaking technologies.

Qualifications

• Proven track record in PLL and power management design, ideally at or near 12nm nodes.
• Strong background in CMOS analog design fundamentals.

Responsabilités

• Design and develop high-speed PLLs (10GHz and above).
• Implement on-chip power management circuits such as LDOs and DACs.
• Collaborate closely with digital, systems, and photonic teams.

Connaissances

PLL Design

Power Management Design

CMOS Analog Design

Problem-Solving Skills

Outils

Cadence

Spectre

Description du poste

IamrecruitingforaSeniorAnalogICDesignEngineeronbehalfofmyclient,agrowingtechnologycompanydevelopingnext-generationsolutionsforhigh-performancedatacommunication.Thepositionisfocusedonhigh-speedPhaseLockedLoopdesignandintegratedpowermanagementwithinadvancedCMOSnodes.

TheSeniorAnalogICDesignEngineerwillcontributetocutting-edgedevelopmentsinenergy-efficientinterconnects.

Key responsibilities:

• Design and develop high-speed PLLs (10GHz and above)
• Implement on-chip power management circuits such as LDOs and DACs
• Collaborate closely with digital, systems, and photonic teams on complex mixed signal integration
• Run simulations, oversee layout, and verify performance of analog building blocks
• Bring industry trends and design innovations into the development cycle

Required experience:

• Proven track record in PLL and power management design, ideally at or near 12nm nodes
• Strong background in CMOS analog design fundamentals
• Proficient with tools like Cadence and Spectre
• Detail-oriented with excellent problem-solving skills

Tobeconsideredforthisopportunity, you will need to have experience in high-speed designs.

This is an excellent opportunity for a Senior Analog IC Design Engineer looking to work on novel technologies in a collaborative and forward-looking environment.

Remote working may be possible for the right candidate, although Italy is preferred.