An Ultra-Low Latency & HFT Intern

Kalray; Montbonnot-Saint-Martin; Remote; EUR 7,800 - 12,000; Full time

Benefits offered by this job

Hybrid work

Meal vouchers

Team building activities

Skiing and other activities

Job summary

Kalray seeks a third-year engineering student to join its DPU Services team for a six-month internship focused on ultra-low-latency networking for financial markets.

You will build measurement prototypes using hardware timestamping and PTP, benchmark kernel-bypass stacks, and evaluate integration of SDN and firewall offloads on DPUs/SmartNICs. English in a technical context is required.

Qualifications

• Develop C/C++ on Linux for low-latency networking projects.
• Familiarity with DPDK, eBPF/XDP or networking SDKs is a plus.
• Strong interest in high-tech hardware/software integrations.

Responsibilities

• Benchmark ultra-low-latency solutions including kernel-bypass stacks.
• Develop an event-to-trade measurement prototype with a market data feed.
• Measure latency and analyze results to guide architectural choices.
• Collaborate with DPU Services team to integrate SDN and firewall offloads.

Skills

C/C++ development

Linux systems

Python automation

Git version control

Networking knowledge

Education

3rd-year engineering student

Tools

NVIDIA DOCA

DPDK

eBPF/XDP

Linux Kernel

Job description

As part of our DPU Services team, which is responsible for all custom networking development based on the SDKs of commercially available SmartNICs and DPUs (NVIDIA ConnectX/BlueField, AMD Solarflare and Pensando, Intel IPU), you will actively contribute to projects involving ultra-low-latency networking for financial markets. You will help identify, through measurement and benchmarking, the solutions that minimize latency in high-frequency trading (HFT) communications, supporting the company’s activities and growth ambitions.

In high-frequency trading, everything happens between the arrival of market data and the transmission of the resulting order: this is known as event-to-trade or tick-to-trade latency. On this critical path, every nanosecond counts: market participants combine kernel-bypass network cards, Layer 1 switches and FPGAs. DPUs can handle everything around this path that must not slow it down, starting with regulatory requirements (MiFID II, DORA): network segmentation (EVPN-VXLAN), filtering, PTP synchronization, as well as packet capture and telemetry. Where should each function be placed, and at what cost in nanoseconds? Your internship will answer this question through prototypes and measurements.

This final-year internship will give you the opportunity to gain first-hand experience in the world of DPUs and SmartNICs, at the intersection of networking, systems and financial markets; build a nanosecond-level measurement setup using hardware timestamping and PTP; develop your high-performance system programming skills; and put the knowledge acquired during your studies into practice in an innovative and stimulating environment.

As such, your main responsibilities will be:

• Benchmark Map out ultra-low-latency solutions: kernel-bypass stacks (AMD Onload, TCPDirect and ef_vi; NVIDIA VMA and XLIO; DPDK, AF_XDP), AMD Solarflare X4, NVIDIA ConnectX-7/BlueField-3 and FPGA cards, hardware and system optimization techniques (CTPIO, cache injection using SDCI on AMD EPYC, core isolation, polling), and reference methodologies (STAC-T0);
• Develop an event-to-trade measurement prototype: a stock market simulator publishes a market data feed over UDP multicast (e.g. ITCH/MoldUDP64), a trading application makes a decision and sends back an order over TCP (OUCH, FIX), and latency is measured on the wire using hardware timestamps, from the incoming packet to the outgoing order;
• Benchmark commercially available solutions using this prototype: median and tail latency (p99, p99.9, max), jitter, small-packet throughput, resilience to market data microbursts, CPU usage and integration effort (standard socket APIs or dedicated APIs);
• Evaluate their ability to integrate SDN and firewall functions: since kernel bypass bypasses the host firewall (iptables), measure in nanoseconds the cost of a VXLAN/EVPN overlay, ACLs and connection tracking offloaded to the eSwitch of a BlueField-3 (OVS-DOCA), compared with FPGA-based approaches and appliances, to determine where each function should be placed: on or off the critical path;
• Present and showcase your work through a benchmark report, architectural recommendations for the team’s solutions, demonstrators and, where appropriate, open-source contributions.

You will also interact with software development teams to address their various needs. This project will provide an overview of all the stages involved in building the software toolchain for Kalray’s IPs, from hardware to application layers.

You will be supervised by DPU Services architects and engineers and will work using agile methods within a rapidly growing team, where your results will directly influence our technical decisions.

REQUIRED AND DEVELOPABLE SKILLS

• C Networking: Ethernet, IP, UDP unicast and multicast, TCP, L2/L3 switching; knowledge of PTP and VXLAN is a plus;
• Development: Modern C and/or C++ on Linux, Python for automation and measurement analysis, Git;
• Systems: Server architecture (CPU, caches, NUMA, PCIe) and Linux kernel mechanisms (interrupts, scheduling, core isolation).
• hardware timestamping and PTP,
• nanosecond-level latency measurement,
• DPU SDKs (NVIDIA DOCA), and network architecture for trading platforms.

Previous experience with DPDK, eBPF/XDP, a network card SDK, lock-free programming or financial markets would be appreciated.

PROFILE

• Third-Third-year engineering student specializing in networking, computer science or embedded systems;
• Curious, ambitious and passionate about high-tech and applications based on new technologies;
• Enjoy working as part of a team and taking initiatives;
• Enthusiastic about being part of a human adventure and working in an agile environment;
• Comfortable in English, particularly in a technical context.

Are you passionate about high-tech and cutting-edge technologies? Do you want to be part of a human adventure and develop in an agile, dynamic and collaborative environment? This internship is for you.

CONTRACT

• Contract type: Internship agreement
• Duration: 6 months
• Compensation: Depending on level of study
• Collective agreement: Metallurgy
• Benefits: Hybrid work, meal vouchers, team building and other activities such as laser tag, escape games, sailing, skiing, go-karting, karaoke and much more!
• Location: Montbonnot(38)

ABOUT KALRAY

Founded in 2008 as a spin-off from CEA, Kalray is a leading European semiconductor company, backed by major industrial investors such as Safran, NXP Semiconductors and Bpifrance. With more than 30 patent families and more than €100 million invested in R&D, our technology is paving the way for a new era in data processing.

Thanks to their patented “manycore” architecture, Kalray’s MPPA intelligent processors (known as DPU or xPU) are capable of managing multiple data streams in parallel – and without bottlenecks – enabling applications that process massive amounts of data to become smarter, more efficient and more energy-efficient, complementing traditional approaches (CPU and GPU).

Kalray’s offering includes hardware and software acceleration solutions, as well as a co-development – or design-ondemand – offering for processors and acceleration solutions optimized for specific uses in high-growth sectors such as data centers, AI gigafactories, 5G networks, Industry 4.0, space and defense, and many others.

Above all, Kalray is a team of passionate, enthusiastic and committed people who place excellence and collaboration at the heart of their work. Whether you are an intern or an apprentice, we will do everything we can to help you fully express your talent, develop your potential and contribute to the company’s success.

Our offices are located near Grenoble, in the French Alps, and we also have additional offices near Nice, in Sophia Antipolis, as well as in Romania.