Senior Analog IC Design Engineer - Hybrid, High-Impact ICs

CoreHW; Finland; Hybrid; EUR 78,000 - 112,000; Full time

Benefits offered by this job

Flexible working hours

Hybrid work arrangement

Comprehensive occupational healthcare

Job summary

CoreHW Oy, a Finnish fabless semiconductor company, seeks a Senior Analog IC Design Engineer to join the Analog and Mixed-Signal Design team. You will work on demanding analog/mixed-signal ICs for international customers and CoreHW’s own IP development.

This hands-on role covers the full design cycle, from specification and transistor-level design through layout support, verification, and silicon validation. It requires deep CMOS understanding and strong English communication.

Qualifications

• Strong professional experience in analog or mixed-signal IC design.

Responsibilities

• Translate system and block-level requirements into analog circuit implementations.
• Design and verify analog/mixed-signal circuits at transistor level.
• Take ownership of blocks through schematic, layout support and sign-off.
• Verify performance across PVT, mismatch, noise and reliability requirements.
• Guide layout to ensure matching, parasitics and reliability.
• Perform post-layout verification and address issues.
• Document design decisions and verification evidence.
• Collaborate with system, RF, digital, verification, layout and test teams.
• Support tape-out, lab characterization and post-silicon debugging.

Skills

Analog design

Mixed-signal design

CMOS circuit design

Schematic design

Layout collaboration

Post-layout verification

Documentation

English communication

Education

B.Sc./M.Sc./Ph.D. in electrical engineering

Tools

Cadence

Synopsys

Job description

CoreHW Oy, a Finnish fabless semiconductor company, seeks a Senior Analog IC Design Engineer to join the Analog and Mixed-Signal Design team. You will work on demanding analog/mixed-signal ICs for international customers and CoreHW’s own IP development.

This hands-on role covers the full design cycle, from specification and transistor-level design through layout support, verification, and silicon validation. It requires deep CMOS understanding and strong English communication.