Senior RTL Design Engineer for Xtensa Processors

Cadence Design Systems; Hämeenlinnan seutukunta; On-site; EUR 16,380 - 21,840; Full time

Job summary

Cadence Design Systems in multiple India locations seeks senior engineers for Xtensa processor RTL design and verification roles. You will implement cores and subsystems, run simulations, and partner with verification teams to meet timing, area, and power goals while mentoring junior engineers.

Requirements include 4+ years in design or verification, strong C/assembly and Verilog/SystemVerilog skills, and a solid background in digital design fundamentals.

Qualifications

• BS/MS in EE/Computer Engineering or similar field.
• Deep understanding of digital design and verification fundamentals.
• Experience as part of a team or mentoring junior engineers.
• Proficiency with Verilog/SystemVerilog and EDA tools.
• Experience in test plans, diagnostics, and coverage analysis.

Responsibilities

• RTL implementation of microprocessor cores and subsystems in Verilog.
• Simulate, debug, synthesize, place & route for timing and area goals.
• Develop test plans, write diagnostics, and analyze coverage.
• Collaborate with Design Verification and EDA teams.
• Assist with debugging and improve overall verification flow.

Skills

Team collaboration

Mentoring junior engineers

Strong communication

Analytical thinking

Problem solving

Education

BS/MS in EE/Computer Engineering

Tools

Verilog

SystemVerilog

EDA tools

UVM

Scripting (Python/Perl/Tcl)

Job description

Cadence Design Systems in multiple India locations seeks senior engineers for Xtensa processor RTL design and verification roles. You will implement cores and subsystems, run simulations, and partner with verification teams to meet timing, area, and power goals while mentoring junior engineers.

Requirements include 4+ years in design or verification, strong C/assembly and Verilog/SystemVerilog skills, and a solid background in digital design fundamentals.