Verification Engineer

Semidynamics; España; Híbrido; EUR 60.000 - 80.000; Jornada completa

Descripción de la vacante

A leading technology company in Barcelona is seeking a Senior Verification Engineer to ensure the correctness of digital designs. Candidates should have a Master or PhD, 8+ years of industrial experience, and proficiency in SystemVerilog and UVM. The role offers flexible schedules, competitive pay, and a dynamic learning environment with additional perks like coffee and free Spanish lessons.

Servicios

Flexible work schedules

Competitive pay

Opportunities for advancement

Candies and coffee

Free Spanish lessons

Formación

• Must have industrial experience of 8+ years.
• Proficiency in SystemVerilog and UVM required.
• C1 English proficiency is essential.

Responsabilidades

• Ensure correctness and functionality of digital designs.
• Utilize verification methodologies and tools for validation.

Conocimientos

Proficiency in SystemVerilog

Experience with UVM

Strong problem-solving skills

Excellent communication abilities

Knowledge of scripting languages (Python, Perl, Bash, TCL)

Industrial experience

Educación

Master or PhD

Herramientas

Simulation tools

Regression tools

Revision control tools (git, svn)

Descripción del empleo

We are hiring! Are you passionate about microprocessor architecture? We need you!

As a Senior Verification Engineer , you will work within the Verification Team and play a crucial role in ensuring the correctness and functionality of complex digital designs at the Register Transfer Level according to the specification, using advanced verification methodologies and tools to validate the designs.

What we offer?

Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (Visa sponsorship if required)

Requirements

• Master or PhD
• English C1
• Industrial experience +8 years
• Proficiency in SystemVerilog and UVM
• Knowledge of scripting languages (Python, Perl, Bash, TCL) and regression tools
• Experience with simulation and simulation tools
• Knowledge of revision control methodology and tools (git, svn)
• Experience in block level and sub-system or top level verification
• Experience with formal and dynamic verification
• Strong problem-solving skills and attention to detail
• Excellent communication and teamwork abilities