Sr. Physical Digital Design Engineer

TN Spain; Barcelona; Presencial; EUR 70.000 - 90.000; Jornada completa

Descripción de la vacante

An established industry player is seeking a Sr. Physical Digital Design Engineer to join their dynamic team in Barcelona. This exciting role involves leading the physical design and implementation of cutting-edge mixed-signal ICs. You will collaborate closely with talented engineers to develop innovative solutions for power management and other advanced applications. The ideal candidate will possess a strong background in ASIC design and digital techniques, with experience in EDA tools. Join this forward-thinking company and contribute to groundbreaking projects that shape the future of technology in a collaborative and supportive environment.

Formación

• 3-5 years of Physical Digital Design experience preferred.
• Strong knowledge of ASIC development process and digital design techniques.

Responsabilidades

• Responsible for physical design and verification of digital/mixed-signal ICs.
• Work closely with design teams for physical implementation and automation.

Conocimientos

Physical Digital Design

ASIC design

Verilog/System Verilog

Programming/Scripting (Perl/TCL/Unix)

Digital Design Techniques

Communication Skills

Team Collaboration

Educación

Advanced degree in Electrical Engineering

Equivalent degree in Computer Science

Herramientas

Cadence

Synopsys

VCS

FPGA Development Tools

Descripción del empleo

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Sr. Physical Digital Design Engineer, Barcelona

Client: Monolithic Power Systems

Location: Barcelona, Spain

Job Category: Other

EU work permit required: Yes

Job Views: 2

Posted: 25.04.2025

Expiry Date: 09.06.2025

Job Description:

Job Summary:

We are looking for a Sr. Physical Digital Design Engineer to join our team of Design Engineers in one of our offices in Europe. This role will be on-site, no remote option is available.

The candidate will be responsible for all aspects of physical design and implementation. In this role, you will participate in the efforts of establishing physical design methodologies and flow automation.

The Physical Design Engineer will be part of the design development team. The candidate will work on the digital design implementation and verification of mixed-signal ICs utilizing standard EDA tools. Products to be designed/verified include power management and mixed signal functions.

MPS products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital camera, automobile and network equipment.

Essential Functions:

• Responsible for physical design, development, & verification of digital / mixed-signal ICs
• Chip & block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, & LVS/DRC to closure
• Work closely with digital/analog design team for physical implementation and custom analog blocks/interface/IPs
• Help build an automated environment for RTL-to-PNR using high level languages and devops-like services

Qualifications:

• Requires advanced degree in Electrical Engineering/Computer Science or equivalent.
• 3-5 years (preferred) of Physical Digital Design experience.
• 2+ years (preferred) ASIC design, verification, or related work experience.
• Good written/verbal communication English skills and strong teamwork collaboration.
• Ability to work independently, follow instructions according to design specifications and execute tasks to hit milestones with quality.
• Strong knowledge of ASIC development process and digital design techniques.
• Experience with programming, scripting and automation languages like Perl/TCL/Unix.
• Strong technical abilities & understanding in these areas: Verilog/System Verilog coding, Synthesis, LEC, CTS, DFT, RC Extraction, and STA closure across multiple process corners, Multipower domain, signal integrity, & power/IR drop analysis, Linting and CDC requirements, Expertise in both hand-written and tool-driven functional/timing ECO, Physical Design Verification methodology to debug LVS/DRC issues at chip/block level, Industry physical tools: Cadence (preferred) or Synopsys.
• Experience with the following is desired: Advanced nodes below 16nm, FinFET SOC design including uC design (ARM/RISCV), Digital on top designs using both bottom-up and top-down flows, Hierarchical STA for chip top designs, Statistical STA, AOCV, SI and noise analysis, Knowledge of power management industry/applications, I/F: I2C, SPI, USB, PMBUS, etc, Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression, Object-oriented programming (Python, Java, etc), VCS: git, svn, Devops, Continuous integration, continuous delivery, FPGA development: Xilinx (preferred), Intel, Lattice, etc.