Senior Signal Integrity Engineer

Semidynamics; Barcelona; Hybrid; EUR 70,000 - 110,000; Full time

Benefits offered by this job

Barcelona office 4 days per week

1 day WFH

1 week remote from anywhere

Competitive package

Job summary

Semidynamics is leading an advanced signal integrity role in a Barcelona-based team. Focus areas include full-stack SI ownership from die to system, PCIe Gen6 PAM4 channels, and LPDDR6 timing budgets.

You will drive 3D extraction, modeling and validation with board, backplane and interconnect considerations. The ideal candidate has 8+ years in high-speed SI, hands-on EM tools, and demonstrated SerDes closure.

Qualifications

• 8+ years in signal integrity for high-speed digital systems, including package-level work.
• Hands-on with at least one 3D EM extraction suite (Ansys HFSS/SIwave, Cadence Clarity/Sigrity, Keysight or equivalent).
• Proven closure on a multi-gigabit SerDes (PCIe Gen5/Gen6 or comparable) and a wide parallel memory interface (DDR5, LPDDR5/6 or HBM).
• Reading a package substrate stackup and bump map; understanding physics implications.
• Python scripting for automation and post-processing.

Responsibilities

• Budgets & feasibility: define and hold loss, crosstalk and jitter budgets across die, package, board and channel.
• Extraction & simulation: perform 3D full-wave and hybrid extraction; run channel simulations with IBIS-AMI.
• Model quality: own passivity, causality, reciprocity and DC accuracy gates on every model.
• Vendor & validation: specify SI requirements and drive characterization with IP/PHY/DRAM/package vendors.

Skills

Signal integrity

Python scripting

3D EM extraction

Tools

Ansys HFSS

HFSS/SIwave

Cadence Clarity

Sigrity

Keysight

Job description

You will own signal integrity end to end — from silicon package, through the board, to the system channel. Senior IC role with architectural influence: you won't be handed a closed spec to verify, you'll help define it.

What you will work on:

• Full-wave extraction and SI closure for a multi-die AI accelerator package
• PCIe Gen6 (PAM4) channel design and compliance margining
• LPDDR6 interface design, timing budget and bus-level closure
• SI ownership on a rack-scale system: backplane, connectors, cabling and interconnect

Responsibilities:

• Budgets & feasibility: Define and hold loss, crosstalk and jitter budgets across die, package, board and channel. Run pre-layout feasibility studies that shape escape routing, stackup and layer assignment before layout is committed.
• Extraction & simulation: Perform 3D full-wave and hybrid extraction of package and board structures, defining port and reference conventions. Run statistical and time-domain channel simulation with IBIS-AMI, interpreted FEC-aware for Gen6.
• Model quality: Own passivity, causality, reciprocity and DC accuracy gates on every model entering the flow.
• Vendor & validation: Define SI requirements in package vendor and OSAT statements of work. Drive model and characterisation requirements with IP, PHY, DRAM and package vendors. Correlate against VNA, TDR and on-die margin scans, and support board bring-up.

Requirements:

• 8+ years in signal integrity for high-speed digital systems, including package-level work
• Hands-on with at least one 3D EM extraction suite — Ansys HFSS/SIwave, Cadence Clarity/Sigrity, Keysight or equivalent
• Proven closure on a multi-gigabit SerDes (PCIe Gen5/Gen6 or comparable) and a wide parallel memory interface (DDR5, LPDDR5/6 or HBM)
• Working knowledge of IBIS, IBIS-AMI and channel simulation methodology
• Comfortable reading a package substrate stackup and bump map, and reasoning about what the physics will do
• Python scripting for automation and post-processing

Nice to Have:

• Silicon package co-design — 2.5D, interposer, chiplet or advanced substrate
• Material characterisation and measurement correlation
• Familiarity with OCP rack-scale platforms and high-speed connector systems
• Automated or AI-assisted engineering flows — PyAEDT, scikit-rf or similar

Why Semidynamics?

• Work for one of Europe’s most promising deep-tech semiconductor scale-ups.
• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 day WFH.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.