Senior Physical Design Engineer - EDA Tools / TCL / Back-End / Synthesis / Place & Route / Flo[...]

European Tech Recruit; Barcelona; Presencial; EUR 70.000 - 90.000; A tiempo parcial

Descripción de la vacante

A leading semiconductor company in Barcelona is looking for multiple Senior Physical Design Engineers. Candidates should have over 6 years of relevant experience and a strong background in EDA tools, with responsibilities including physical design verification and participation in tape-outs. The role offers competitive salary and flexible work schedules.

Formación

• 7+ years of experience in synthesis, place & route flows, floorplanning.
• Experience with physical design verification, timing closure, and DRC/LVS.
• Have been part of at least 2 tape outs.

Responsabilidades

• Participate in tape-outs and contribute to physical design verification.
• Work on timing closure and physical verification processes.
• Collaborate with a team on backend/physical design tasks.

Conocimientos

Synthesis

Place & Route

Floorplanning

EDA Tools

TCL Scripting

Educación

BSc, MSc or PhD in Computer Science

Herramientas

Synopsys

Cadence

Mentor

Descripción del empleo

Overview

Senior Physical Design Engineer - EDA Tools / TCL / Back-End / Synthesis / Place & Route / Floorplanning

Senior Physical Design Engineer - EDA Tools / TCL / Back-End / Synthesis / Place & Route / Floorplanning

Opportunity

We are partnering with an exciting Barcelona-based semiconductor company seeking multiple Senior Physical Design Engineers to join on a permanent basis, working fully onsite in central Barcelona. The company has aggressive growth plans and aims to hire at least 20 engineers over the next 18 months. Visa sponsorship is available if needed, and free Spanish lessons are provided to help you assimilate in Spain. International applicants are encouraged.

Responsibilities

• Are you a Senior Backend / Physical Design Engineer looking for your next challenge?
• Have 6+ years of experience in synthesis, place & route flows and floorplanning and wireplanning?
• Participate in tape-outs and contribute to physical design verification and sign-off processes, including timing closure and physical verification (DRC, LVS)

Qualifications

• BSc, MSc or PhD in Computer Science
• EDA Tools experience including Synopsys / Cadence / Mentor
• Scripting (TCL) experience
• 7+ years experience Synthesis, Place & Route flows, Floorplanning and Wireplanning
• Been a part of at least 2 tape outs
• Knowledge of physical design verification and sign-off methodologies

Benefits & Application

In return you'll receive an excellent yearly salary, flexible work schedules, and very good career progression, whilst working within a team of extremely talented individuals.

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Seniority level

Mid-Senior level

Employment type

Part-time

Industries

Computer Hardware Manufacturing, Semiconductor Manufacturing, and Software Development