Senior Photonics Layout Engineer

Ipronics; Valencia; Presencial; EUR 70.000 - 95.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Permanent full-time position

Flexible working hours

December 24th and 31st off

One extra day off during your birthday

Private health insurance

Life insurance

Pension plan included

Flexible compensation plan (restaurant

transport, and childcare vouchers

Descripción de la vacante

iPronics seeks a Senior Photonics Layout Engineer to advance photonic IC design across SiPh and III-V platforms. You will craft complex layouts, generate GDS files, and drive tape-out activities with foundries, ensuring manufacturability and cross-functional collaboration.

The role requires strong Python scripting, experience with KLayout/GDSFactory/Calibre, and fluent English. Join a dynamic Photonics Department delivering cutting-edge integrated photonics solutions.

Formación

• Minimum 5+ years in SiPh/III-V photonics or IC layout.
• Experience with layout tools and physical verification.
• Knowledge of foundry PDKs and tape-out flows.
• Fluent English (C1 level) and strong team communication.

Responsabilidades

• Design complex layouts and generate GDS files for photonic ICs.
• Perform layout reviews and physical verification (DRC and checks).
• Ensure compatibility with foundry PDKs and rules.
• Develop main and test die GDS layouts for tape-out schedules.
• Translate requirements into manufacturable photonic IC layouts.
• Drive tape-out activities and coordinate with foundries.
• Collaborate with cross-functional teams for testability and integration.

Conocimientos

Python programming

GitHub

English fluency

Technical communication

Educación

BSc/MSc in Telecommunication Engineering or Physics

Herramientas

KLayout

GDSFactory

Calibre

Descripción del empleo

iPronics is seeking a Senior Photonics Layout Engineer to join our Photonics Department, working on both Silicon Photonics (SiPh) and III-V photonic technologies for integrated photonic systems.

Main Responsibilities

As part of the Layout Team, you will play a key role in photonic circuit layout and tape-out activities across SiPh and III-V platforms.

• Designing complex layouts and generating GDS files for SiPh and III-V photonic integrated circuits.
• Performing layout reviews and physical verification, including DRC and other applicable checks.
• Ensuring compatibility between cross-sections, foundry PDKs, design rules, and custom-developed photonic components.
• Developing main and test die GDS layouts, ensuring commitment to tape-out schedules and deadlines.
• Translating system and device requirements into manufacturable photonic IC layouts.
• Driving layout-related tape-out activities and technical communication with foundries.
• Collaborating with cross-functional teams to ensure testability, manufacturability, and system integration.

Desired Skills & Experience

• BSc or MSc degree (PhD preferred) in Telecommunication Engineering, Physics, or a related field, with a focus on Integrated Photonics.
• 5+ years of experience in SiPh, III-V photonics, IC layout, or a related field.
• Strong experience with layout tools such as KLayout, GDSFactory, or equivalent. Experience with Calibre or other physical verification tools is a plus.
• Experience with foundry PDKs, DRC, and photonic tape-out flows.
• Solid programming skills in Python and experience with GitHub.
• Basic knowledge of semiconductor manufacturing processes such as lithography, etching, and metal deposition is a strong plus.
• Reliable, proactive, and self-motivated, with strong technical communication and teamwork skills.
• Fluency in English (C1 level or higher).

What we offer

• Permanent full-time position
• Flexible working hours
• December 24th and 31st off
• One extra day off during your birthday month
• Private health insurance and life insurance
• Pension plan included
• Flexible compensation plan (restaurant tickets, transport, and childcare vouchers)