Senior Mixed Signal Verification Engineer

Robert Bosch Group; Valencia; Presencial; EUR 45.000 - 65.000; Jornada completa

Descripción de la vacante

A leading technology company in Comunidad Valenciana is seeking a Senior Mixed Signal Verification Engineer to develop accurate behavioral models and verify mixed-signal circuits. The ideal candidate will have a Master’s or Bachelor’s degree in Electrical/Electronics/Computer Engineering, a minimum of 5 years of experience, and strong skills in Verilog/SystemVerilog. You’ll work closely with system architects and designers, ensuring high-quality validation and debugging in a challenging environment.

Formación

• Minimum 5 years of relevant industry experience.
• Experience in developing validation plans and analyzing test results.
• Ability to work in a fast-paced, multi-site, multi-group environment.

Responsabilidades

• Develop accurate behavioral models for mixed-signal circuits.
• Verify performance against circuit-level simulations.
• Collaborate with architects and designers on specifications.

Conocimientos

Behavioral modeling

Debugging skills

Problem-solving

Team collaboration

Communication skills

Educación

Masters or Bachelor's in Electrical/Electronics/Computer Engineering

Herramientas

Verilog/SystemVerilog

UVM

DSP techniques

Python

Descripción del empleo

Senior Mixed Signal Verification Engineer

• Develop accurate behavioral models for mixed-signal circuits
• Verify the performance and accuracy of the developed models against circuit-level simulations and measurements.
• Collaborate closely with system architects and analog/digital designers to understand circuit specifications, design intent, and performance requirements
• Develop mixed signal verification strategies for state-of-the-art SoCs containing high speed digital circuits and sensitive analog/RF circuits.
• Implement verification plans and track their coverage
• Develop and run system simulations to verify the design, analyze performance, power and timing, and uncover bugs.
• Replicate root causes and debug issues in the pre-silicon environment.
• Find and implement corrective measures to resolve failing tests.
• Maintain and improve existing functional verification infrastructure and methodology.
• Implement/maintain post processing scripts for assessing system performance
• Development of tools for automated generation of verification reports and regression management.

You should possess a Masters or Bachelor's degree in Electrical/Electronics/Computer Engineering, with at least 5 years of relevant experience in the industry.

• Experience in developing high quality validation plans, collecting and analyzing the test results and being able to debug the failures to RTL/gate/schematic level
• Strong problem-solving and teamwork skills, and strong verbal and written communication skills
• Ability to produce results in a challenging, fast-paced, multi-site, multi-group environment
• Good working knowledge of Verilog/SystemVerilog is a must.
• Good working knowledge of UVM.
• Good working knowledge of DSP techniques used for assessing performance of Radar systems
• Experience in setting up, running and debugging Gate Level simulations
• Work experience with at least one other verification aspects like System modeling, Formal verification etc. would be an added advantage.
• Proficiency in scripting languages and utilities including Make, Python, etc. will be a bonus.
• Should be able to contribute as Individual Contributor or technically leading a group of team members as per requirements