Senior Digital IC Verification Engineer - RISC-V

ic resources; Madrid; Presencial; EUR 50.000 - 70.000; Jornada completa

Descripción de la vacante

An exciting opportunity awaits as a digital verification engineer, where you will work on cutting-edge RISC-V technology within the semiconductor industry. This role offers the chance to contribute to advanced technology nodes and complex ASIC designs, utilizing your expertise in UVM environments and System Verilog. Join a dynamic team and play a pivotal role in shaping the future of semiconductor technology. If you have a passion for innovation and a strong background in digital verification, this position is perfect for you, offering a chance to make a significant impact in a rapidly evolving field.

Formación

• 5+ years of experience in digital verification with UVM.
• Strong skills in System Verilog for ASIC IP verification.

Responsabilidades

• Contribute to advanced RISC-V designs and technology nodes.
• Set up ASIC Verification environments and methodologies.

Conocimientos

UVM environments

System Verilog

ASIC design

Verification Metrics definition

Coverage analysis

Debugging skills

RISC-V knowledge

SOC verification

Educación

Masters in Electronics

PhD in Microelectronics

Herramientas

vManager

vPlan

Descripción del empleo

Exciting opportunity to work on the latest cutting edge RISC-V technology in the semiconductor industry.

In this new role as a digital verification engineer, you will have the opportunity to contribute to advanced technology nodes, consisting of RISC-V designs, ARM & CPU architecture, PCIe protocols, and machine learning.

I am looking to speak with digital verification engineers with 5+ years of experience who have the following skills:

Required:

• Masters or PhD degree in Electronics / Microelectronics or a similar field
• 5+ years' experience in UVM environments & processes
• System Verilog for IP / SOC Verification of digital ICs / ASIC IP or chips
• Complex ASIC designs & architecture for advanced technology nodes
• Verification Metrics definition, Coverage analysis, and debugging skills
• Knowledge and experience in setting up an ASIC Verification environment, methodology, and flow
• vManager, vPlan and Regressions, etc.
• RISC-V / CPU / GPU (this is a bonus, not required)
• Knowledge of SOC verification is also a bonus
• Visa sponsorship can be offered if required (dependent on experience / qualifications)

Senior Engineer • Madrid, Community of Madrid