Research Engineer: RTL OoO Core for RISC-V HPC

Barcelona Supercomputing Center; Madrid; Presencial; EUR 55.000 - 75.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Restaurant tickets

Private health insurance

Relocation support

Flexible working hours

Descripción de la vacante

Barcelona Supercomputing Center (BSC-CNS) in Barcelona seeks a Research Engineer in the Computer Sciences Department to join an active computer architecture group. You will design and develop a high-end out-of-order RISC-V core for HPC applications, contributing to the European DARE project and to an energy-efficient post-exascale ecosystem.

The role covers RTL design, verification with CoCoTB and Python models, performance benchmarking, tool development, and documentation.

Formación

• BS or MS in Telecommunication, Electronics, CS, or Computer Engineering.
• Strong knowledge of logic circuits and digital design.
• Proficiency in SystemVerilog and RTL design.
• Familiarity with the RISC-V specification and open-source RTL tools.
• Experience with Linux, Python and version control tools.

Responsabilidades

• Research architectural techniques and develop RTL hardware for OoO core design.
• Design RTL structures for RISC-V CPU architectures.
• Implement control logic and data paths in SystemVerilog.
• Verify modules with CoCoTB and Python hardware modeling.
• Evaluate performance via simulations and benchmarking.
• Document design specifications and test plans.

Conocimientos

RISC-V Architecture

SystemVerilog

Python

CoCoTB

Git

Linux

C/C++

RTL Design

Educación

BS or MS in Telecommunication, Electronics, CS, or Computer Engineering

Herramientas

SystemVerilog tooling

RTL simulation tools

Linux tooling

Descripción del empleo

Barcelona Supercomputing Center (BSC-CNS) in Barcelona seeks a Research Engineer in the Computer Sciences Department to join an active computer architecture group. You will design and develop a high-end out-of-order RISC-V core for HPC applications, contributing to the European DARE project and to an energy-efficient post-exascale ecosystem.

The role covers RTL design, verification with CoCoTB and Python models, performance benchmarking, tool development, and documentation.