Performance Modelling Engineer

Semidynamics; Barcelona; Presencial; EUR 65.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

4 days per week in Barcelona

1 day WFH

Work from anywhere 1 week

Competitive package

Descripción de la vacante

Semidynamics is building a new generation of high-performance computing products for AI based on RISC-V. The Performance Modelling Engineer contributes to performance analysis and modelling of components, instrumenting simulators, and validating results in a multidisciplinary team in Barcelona.

Expect deep technical discussions, ownership of components, and iterative method development. The role emphasizes automated tooling, close collaboration with architecture and software teams, and growth

Formación

• Strong C/C++ and scripting skills (Python, Bash, TCL) for simulator tooling.
• Linux proficiency and experience with profiling tools (perf, VTune, Nsight Systems, Perfetto).
• Experience building cycle-accurate simulators or analytical models.

Responsabilidades

• Take responsibility for design and delivery of performance models or analysis work.
• Flag issues early with proposed solutions and collaborate with adjacent teams.
• Contribute to technical reviews and improve tooling and methods.

Conocimientos

C/C++

Python

Linux

Profiling

Simulator tooling

Performance modelling

Workload analysis

xPU architecture

Herramientas

pybind11

perf

VTune

Nsight Systems

Descripción del empleo

Semidynamics is building a new generation of high-performance computing products for AI based onRISC-V. The company designs custom, scalable silicon for compute-intensive applications, wheresoftware, architecture, modelling, and hardware validation meet. The work sits close to the product's technical foundations. Engineers are exposed to real architectural trade-offs, performance limits, and silicon-facing decisions earlier and more directlythan in most roles.This is demanding engineering work with a direct path into the silicon that will run the nextgeneration of HPC/AI computing. The Performance Modelling Engineer contributes directly to the work that shapesSemidynamics' products. The role carries responsibility for its assigned scope, the technicaldecisions made within that scope, and the quality of the results delivered. The engineer works in a multidisciplinary team where hardware, software, and AI specialists work side by side. Decisions are expected to follow the strongest technical argument, supported bycollaboration, direct feedback, and shared credit. Semidynamics typically looks for around 2-5 years of relevant experience for this level. This range isa guide rather than a strict cutoff: what matters most is the depth of skill demonstrated in the technical interview. At this level, the engineer is responsible for the performance analysis and modelling of individual components from start to finish, from instrumenting simulators to signing off on the results. The role involves limited day-to-day supervision: choosing the approach for a component, validating the result, and raising issues early with a proposed path forward. This is where the technical foundation is built: simulator instrumentation, workload analysis, cycle-accurate modelling, and the ability to connect software behaviour with hardware events.

Why Semidynamics?

• Work at one of Europe’s most promising deep-tech semiconductor start up - from silicon to systems - Semidynamics.
• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 day WFH.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.

Requirements

REQUIRED TECHNICAL SKILLS

• Strong skills in C/C++ and scripting (Python, Bash, TCL), including interoperability between C/C++ and scripts (for example, with pybind11) for simulator tooling.
• Working knowledge of Linux and standard profiling tools (perf, VTune, Nsight Systems, Perfetto, Intel Advisor, FlameGraph).
• Profiling of applications, including visualising execution behaviour through sequence diagrams and class diagrams.
• Able to instrument simulators to collect performance counters, including at the RISC-V instruction level.
• Correlates hardware events with software behaviour and builds repeatable test setups for a range of workloads.
• Strong understanding of single-node xPU architecture, including pipeline stages and memory behaviour.
• Basic knowledge of multi-xPU/multi-node system topology (NVLink, PCIe);
• Experience building cycle-accurate simulators or analytical models.
• Understanding of design and testing across RTL, software, FPGA, and silicon.
• Some experience with test automation at scale, covering multicore execution, high throughput, high data volume, tracing, and analysis methods.

DESIRED SKILLS

• Some experience with RTL design and testing based on simulation and synthesis.
• Some knowledge of Roofline Modelling and profiling of kernels and call stacks.
• Trace-based analysis.
• Some knowledge of the silicon life cycle (early design, design and verification testing, post-silicon testing).
• Some experience with JIT-based, event-based, or cycle-based modelling.
• RISC-V Vector assembly and architecture-based optimisation.
• A PhD in a relevant technical field is a plus.

PROFILE AND SOFT SKILLS

Autonomy: The engineer is responsible for the approach to their component, choosing the method, the tools, and the validation plan without needing sign-off beforehand. Escalation happens only when a decision affects scope, deadlines, or another team's work, not for routine technical choices within the component itself.

Impact: The work covers one or a small number of components, from specification through to sign-off. Quality and correctness within that scope rest entirely with the engineer, who is the person others turn to with questions about it.

Strategic vision: The engineer understands how their component supports the current product's performance goals, and raises it when a design choice works against them, though setting direction beyond that scope is not expected at this level.

RESPONSIBILITIES ON THIS TEAM

• Take responsibility for the design and delivery of assigned performance models or analysis work from start to finish.
• Flag issues early, with a proposed solution rather than just a warning.
• Act as the main point of reference for the team on assigned components.
• Work with adjacent teams, such as architecture and software, to resolve shared issues.
• Identify gaps in tooling or method and propose concrete improvements.
• Take an active part in technical reviews, contributing real input.

GROWTH AT THIS LEVEL

• Feedback from: the direct manager, informed by technical input from senior peers who have reviewed the engineer's work.
• Review frequency: a formal check-in at least twice a year, alongside ongoing informal feedback.
• What growth looks like at this level: taking on more components independently, extending analysis from single-node xPU topics into multi-xPU and interconnect questions, and beginning to support L1/L2 engineers informally on tooling or method. Growth is shown through consistent execution, care for the quality of the resulting work, responsiveness to feedback, and the ability to explain technical choices clearly, not through technical output alone.