Microelectronic Design Engineer

JR Spain; Tres Cantos; Presencial; EUR 40.000 - 80.000; Jornada completa

Descripción de la vacante

An established industry player is seeking a Microelectronic Design Engineer to join their innovative team in Tres Cantos. This exciting role involves designing and implementing advanced FPGA and ASIC solutions, with a focus on high-level requirements analysis and low-level design specifications. The ideal candidate will have a strong engineering background, particularly in Microelectronics, and be proficient in VHDL, Verilog, and various scripting languages. Join this dynamic firm where your contributions will play a crucial role in cutting-edge projects that shape the future of technology and compliance in the aerospace sector.

Formación

• 3+ years of experience in FPGA or ASIC design.
• Strong background in Microelectronics and hardware description languages.
• Proficiency in scripting and programming languages.

Responsabilidades

• Analyze and synthesize high-level requirements for design.
• Implement RTL VHDL/Verilog with simulations.
• Automate tasks using scripting languages.

Conocimientos

VHDL

Verilog

Python

C/C++

TCL

Bash

FPGA design

ASIC design

Digital signal processing

Control theory

Educación

High degree in engineering

Telecommunication Engineering

Industrial Engineering

Herramientas

Synopsys

Mentor

Microsemi

Xilinx

Altera

MATLAB

Simulink

Descripción del empleo

Social network you want to login/join with:

Microelectronic Design Engineer, Tres Cantos

Client: Airbus

Location: Tres Cantos

Job Category:

Other

-

EU work permit required:

Yes

Job Reference:

910670379003936768032460

Job Views:

1

Posted:

31.03.2025

Expiry Date:

15.05.2025

Job Description:

Requirements: High degree in engineering, preferably Telecommunication Engineering or Industrial Engineering, and a strong background in Microelectronics. A minimum of 3 years of experience in FPGA or ASIC design. Previous experience in space projects is a plus. Knowledge in Hardware description languages VHDL and Verilog is essential; SystemVerilog is a plus. Knowledge in Mixed-Signal ASIC development and high-level synthesis is advantageous. Proficiency in scripting languages Python, TCL, Bash, and programming languages C/C++ is required. Experience with ASIC and FPGA design tools from Synopsys, Mentor, Microsemi, Xilinx, Altera. Knowledge in digital signal processing, digital image processing, and control theory is beneficial. Familiarity with model-based design, MATLAB, and Simulink environment is a plus.

Main tasks:

• Analysis and synthesis of high-level requirements
• Creation of low-level design specifications based on higher-level requirements
• Architecture definition of the design
• RTL VHDL/Verilog implementation with unit and system-level simulations
• HDL code coverage analysis
• Synthesis and layout of the design
• Timing analysis and worst-case analysis
• Automation of tasks via scripting
• Interaction with other design teams for implementation, verification, and validation
• Implementation of control and digital signal processing algorithms in FPGAs and ASICs

This role requires awareness of potential compliance risks and a commitment to acting with integrity, underpinning the company's success, reputation, and sustainable growth.

Company: Computadoras, Redes e Ingeniería, SA

Contract Type: Permanent Contract / CDI / Unbefristet / Contrato indefinido

Experience Level: Professional / Expérimenté(e) / Professionell / Profesional

Job Family: Elec.Electron.&Electromag, Optics & Optron.