Lead Full-Chip Physical Design Architect

Aion Silicon; Barcelona; Híbrido; EUR 157.465 - 227.450; Jornada completa

Descripción de la vacante

Aion Silicon is seeking a Principal Physical Design Engineer to lead full-chip implementation of complex SoCs/ASICs. You will own the complete flow from RTL handoff to GDSII, collaborating with RTL, STA, DFT, packaging and foundry partners globally.

The role requires 10+ years in physical design, leadership experience, and strong skills in 7nm/5nm nodes, with a track record of successful tape-outs and impactful stakeholder engagement.

Formación

• 10+ years of Physical Design experience with a proven track record of full-chip delivery.
• Advanced technology nodes, including 7nm, 5nm and below.
• Experience delivering multiple complex SoC or ASIC tape-outs.
• Demonstrated leadership experience mentoring and developing engineers.
• Strong customer engagement and stakeholder management skills.
• Excellent communication skills with the ability to influence technical direction across multiple teams.

Responsabilidades

• Lead full-chip physical implementation for complex SoC and ASIC designs.
• Define and drive chip-level physical design strategies, methodologies and best practices.
• Coordinate closely with RTL, STA, DFT, Packaging, Foundry and EDA partners to achieve successful design closure.
• Mentor and coach Physical Design engineers, supporting capability development across the team.
• Review and approve block-level physical design deliverables before integration.
• Lead technical reviews, debug sessions and closure activities.
• Support recruitment activities and contribute to building a world-class Physical Design team.
• Represent Aion Silicon at universities, conferences and industry events, sharing technical expertise and promoting innovation.
• Ensure the team remains at the forefront of industry methodologies, tools and advanced-node technologies.

Conocimientos

10+ years PD experience

Advanced nodes 7nm/5nm

Leadership/mentoring

Customer engagement

Communication skills

Educación

Master's or PhD in engineering

Herramientas

Synopsys ICC2

Fusion Compiler

PrimeTime

StarRC

ICV

Cadence Innovus

Cadence Tempus

Cadence Voltus

Cadence Genus

Mentor Calibre

Descripción del empleo

Aion Silicon is seeking a Principal Physical Design Engineer to lead full-chip implementation of complex SoCs/ASICs. You will own the complete flow from RTL handoff to GDSII, collaborating with RTL, STA, DFT, packaging and foundry partners globally.

The role requires 10+ years in physical design, leadership experience, and strong skills in 7nm/5nm nodes, with a track record of successful tape-outs and impactful stakeholder engagement.