Lead DMS Verification Engineer – Mixed-Signal SoCs

Bosch Group; Valencia; Presencial; EUR 65.000 - 95.000; Jornada completa

Descripción de la vacante

Bosch Group in Valencia seeks an experienced DMS Verification Engineer to join the engineering team. You will collaborate with system architects and designers to develop verification strategies for Mixed-Signal SoCs, drive plans, and ensure robust verification flows.

The role emphasizes leadership, cross-site collaboration, and hands-on verification across RTL to schematic levels, with a focus on delivering high-quality mixed-signal verification.

Formación

• Bachelor's or Master's degree in Electrical/Electronic Engineering or related field.
• Proven experience in developing validation plans, analyzing test results, and debugging failures at RTL, gate, and schematic levels.
• Strong working knowledge of SystemVerilog/Verilog and UVM.
• Experience setting up, running, and debugging Gate-Level Simulations (GLS).
• Good understanding of DSP techniques and analog schematics.
• Strong problem-solving, communication, and teamwork skills.
• Professional working proficiency in English (C1 level minimum).
• Valid work authorization for the European Union is required.

Responsabilidades

• Drive specification reviews to generate initial verification plans using Vmanager.
• Define verification strategies, including partitioning between DMS and DV, and model versus schematic equivalence.
• Plan and manage resources, schedules, and progress tracking, identifying and addressing potential showstoppers.
• Implement verification plans, run regressions, and track functional and code coverage.
• Verify the accuracy and performance of behavioral models against circuit-level simulations and measurements.
• Perform root-cause analysis and debug issues down to RTL, gate, and schematic levels.
• Maintain and improve functional verification infrastructure, flows, and UVM methodologies.
• Provide technical leadership, mentorship, and support across multi-site engineering teams.

Conocimientos

SystemVerilog/Verilog

UVM

GLS (Gate‑Level Simulations)

DSP techniques

Analog schematics understanding

English proficiency (C1)

Teamwork

Problem solving

System Modeling

Formal Verification

Python

Make

Shell

Educación

Electrical/Electronic Engineering

Herramientas

Vmanager

Python

Make

Shell

Descripción del empleo

Bosch Group in Valencia seeks an experienced DMS Verification Engineer to join the engineering team. You will collaborate with system architects and designers to develop verification strategies for Mixed-Signal SoCs, drive plans, and ensure robust verification flows.

The role emphasizes leadership, cross-site collaboration, and hands-on verification across RTL to schematic levels, with a focus on delivering high-quality mixed-signal verification.