Lead DFT & Post Silicon Validation Engineer

microTECH Global Limited; España; Presencial; EUR 70.000 - 90.000; Jornada completa

Descripción de la vacante

A leading technology firm in Spain is seeking a Lead DFT & Post Silicon Validation Engineer to oversee the DFT implementation process. You will lead engineering teams, collaborate with validation teams, and ensure high-quality SoCs for mass production. The ideal candidate holds a relevant degree and has experience with high-performance SoCs. Strong knowledge in DFT methodologies and excellent leadership skills are essential for success in this role. This position offers the opportunity to work with cutting-edge technology and drive team innovation.

Formación

• Proven experience with multiple tape-outs of high-performance SoCs or SiPs for mass production.
• Strong background in post-silicon test optimization and yield analysis.
• Experience in defining and implementing test strategies for high-volume production.

Responsabilidades

• Lead and mentor the DFT and Post-Silicon engineering teams.
• Define and implement DFT architectures for testability and manufacturability.
• Develop and implement test plans and strategies at all product development stages.

Conocimientos

Design for Testability (DFT)

Team Leadership

Test Development

Scripting (Shell, Tcl, Python3)

Educación

Bachelor’s, Master’s, or PhD in Computer Science

Herramientas

SystemVerilog

Verilog

Tessent

Descripción del empleo

Lead DFT & Post Silicon Validation Engineer

Location: Spain

Type: Permanent

We are hiring! Are you passionate about Design for Testability (DFT) for complex SoCs and SoC chiplets in package? We need you! As a Senior DFT and Post‑Silicon Lead, you will own the DFT implementation process, ensuring seamless integration with test and post‑silicon validation teams. You will work with cutting‑edge technology, collaborating closely with external IP providers, EDA vendors, and internal teams to deliver high-quality, high-performance SoCs or SiPs for mass production.

Key Responsibilities

• Leadership & Team Management
• Lead and mentor the DFT and Post‑Silicon engineering teams to drive innovation and efficiency.
• Provide technical direction, ensuring alignment with organizational goals.
• Foster a culture of continuous improvement and collaboration.
• DFT Strategy & Execution
• Define and implement DFT architectures to improve testability, debug capabilities, and manufacturability.
• Ensure proper insertion of DFT features such as scan chains, BIST (Built-In Self-Test), and JTAG interfaces.
• Optimize DFT methodologies to minimize test time, reduce cost, and improve quality/yield.
• Test Development & Implementation
• Develop and implement test plans and test strategies at silicon, package, and system levels.
• Define and develop automated test solutions for production and characterization.
• Ensure test coverage for all product development stages, from pre‑silicon to mass production.
• Guarantee high yield on the final solution while considering chiplet complexities.
• Cross‑Functional Collaboration
• Work closely with design, validation, packaging, and operations teams to ensure seamless integration of testing and manufacturability.
• Collaborate with product management to ensure alignment with customer requirements and timelines.
• Process Improvement & Innovation
• Continuously explore and implement new DFT methodologies and manufacturing processes.
• Lead initiatives for cost reduction, efficiency improvements, and quality enhancements in test and production.

Reporting Structure

• Reports to: Physical Implementation Team Manager
• Receives reports from: DFT and Post‑Silicon team members

Requirements

• Bachelor’s, Master’s, or PhD in Computer Science, Electrical Engineering, or a related field.
• Proven experience with multiple tape‑outs of high-performance SoCs or SiPs for mass production.
• Strong background in post‑silicon test optimization and yield analysis.
• Experience in defining and implementing test strategies for high-volume production.
• Proficiency in RTL and testbench development using SystemVerilog and Verilog.
• Strong scripting skills (Shell, Tcl, Python3).
• Hands‑on experience with Tessent and SSN methods integrated with leading EDA design flows for advanced technology nodes is a plus.

If you would like to learn more, please email [e-mail] directly.