Senior DFT Architect & Lead - Chip Test Strategy

Aion Silicon; Barcelona; Presencial; EUR 70.000 - 95.000; Jornada completa

Descripción de la vacante

A leading technology firm based in Barcelona is seeking an experienced DFT Engineer to lead chip-level Design for Test execution. The ideal candidate will drive DFT delivery from architecture definition through pattern generation and silicon bring-up, ensuring high-quality implementation and effective debug. With 10+ years of experience and expertise in DFT tools, this role calls for strong project management skills and the ability to innovate. This position is part of a global team with flexible location options.

Formación

• 10+ years of experience in Design for Test (DFT) engineering.
• Solid understanding of DFT principles and architecture.
• Recognized as a problem solver within a DFT team.

Responsabilidades

• Lead DFT strategy definition and implementation.
• Solve complex problems and provide innovative solutions.
• Collaborate with team members and engineering management.

Conocimientos

Expertise with DFT tools from Siemens or Synopsys

Strong experience in ATPG and test coverage improvements

Problem-solving

Project management skills

Educación

Degree/Masters or PhD in a relevant subject

Descripción del empleo

A leading technology firm based in Barcelona is seeking an experienced DFT Engineer to lead chip-level Design for Test execution. The ideal candidate will drive DFT delivery from architecture definition through pattern generation and silicon bring-up, ensuring high-quality implementation and effective debug. With 10+ years of experience and expertise in DFT tools, this role calls for strong project management skills and the ability to innovate. This position is part of a global team with flexible location options.