Digital IC Designer: RTL, Cadence Expert, Timing

TMRW; Madrid; Presencial; EUR 50.000 - 75.000; Jornada completa

Descripción de la vacante

The TMRW Foundation SILICON in Barcelona, Spain, seeks a mid-senior Digital IC Designer to drive RTL design, verification, and implementation for cutting-edge IC projects. You will employ Cadence tools to meet performance, power, and area targets across complex digital blocks.

Responsibilities include RTL coding in Verilog/VHDL, functional verification, and timing sign-off using Tempus, Genus, Innovus and NCLaunch/Incisive.

Formación

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• Proven experience in digital IC design with a strong project portfolio.
• Expertise in the Cadence digital design flow including Virtuoso, Genus, Innovus, Tempus and verification tools.
• Familiarity with other industry-standard EDA tools (Synopsys, Mentor Graphics) is a plus.
• Proficiency in hardware description languages (Verilog, VHDL).

Responsabilidades

• RTL Design & Development: Develop and implement RTL code using VHDL/Verilog per design specs.
• Simulation and Verification: Perform functional verification and simulation using Cadence tools.
• Synthesis and Implementation: Handle synthesis, floorplanning, placement, clock tree, routing.
• Timing Analysis and Signoff: Conduct static timing analysis and timing closure with Cadence Tempus.
• Physical Verification: Run DRC/LVS to prepare designs for fabrication (tape-out).
• Collaboration: Work with cross-functional teams with architects, analog designers, and layout engineers.
• Documentation: Create design docs, technical reports, and test plans.

Conocimientos

Verilog

VHDL

Digital IC design

Scripting (Tcl, Python, Perl)

Analytical skills

Educación

Bachelor's or Master's in Electrical/Computer Engineering or related field

Herramientas

Cadence Genus

Cadence Innovus

Cadence Tempus

Cadence Virtuoso

Cadence NCLaunch/Incisive/SimVision

Cadence Pegasus

Synopsys

Mentor Graphics

Descripción del empleo

The TMRW Foundation SILICON in Barcelona, Spain, seeks a mid-senior Digital IC Designer to drive RTL design, verification, and implementation for cutting-edge IC projects. You will employ Cadence tools to meet performance, power, and area targets across complex digital blocks.

Responsibilities include RTL coding in Verilog/VHDL, functional verification, and timing sign-off using Tempus, Genus, Innovus and NCLaunch/Incisive.