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Digital Design Engineer

TechTeamz

Tarragona

A distancia

EUR 60.000 - 80.000

Jornada completa

Hace 4 días
Sé de los primeros/as/es en solicitar esta vacante

Descripción de la vacante

A leading tech firm is seeking a Senior ASIC Hardware Design Engineer to contribute to high-performance digital chip designs. The ideal candidate must have over 5 years of ASIC digital design experience, along with strong proficiency in SystemVerilog and experience with high-speed memory interfaces. This position offers a remote work opportunity based in Spain or Egypt.

Formación

  • 5+ years of ASIC digital design experience is essential.
  • Strong knowledge of SoC microarchitecture, clocking, and reset strategies required.
  • Proficiency in SystemVerilog and RTL development is necessary.

Responsabilidades

  • Conduct end-to-end ASIC design for digital IP like memory interfaces.
  • Implement RTL in Verilog/SystemVerilog.
  • Collaborate with verification and architecture teams is a key task.

Conocimientos

ASIC digital design experience
SoC microarchitecture knowledge
Proficient in SystemVerilog
Experience with high-speed memory interfaces

Herramientas

ModelSim
Synopsys

Descripción del empleo

Senior ASIC Hardware Design Engineer (Spain / Egypt)

Work Location :

Remote (Spain or Egypt) | Hybrid optional

Employment Type :

Full-time Contractor via TechTeamz

Project Area :

High-performance digital chip design

We're looking for

An experienced ASIC Design Engineer to work on cutting-edge high-speed interface technologies. This is a challenging and rewarding role for someone skilled in digital design, system integration, and RTL development.

Responsibilities :

  1. End-to-end ASIC design for digital IP (e.g., memory interface, interconnect, etc.)
  2. RTL implementation in Verilog / SystemVerilog
  3. Collaborate with verification, physical design, and architecture teams
  4. Drive synthesis, linting, CDC, and integration efforts

Requirements :

  1. 5+ years of ASIC digital design experience
  2. Strong knowledge of SoC microarchitecture, clocking, and reset strategies
  3. Proficient in SystemVerilog, Verilog, and simulation tools (ModelSim, Synopsys, etc.)
  4. Prior experience with high-speed memory or interface IP (e.g., PCIe, DDR, HBM) is a plus

If you are interested, send over your CV.

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