Design Verification Engineer

TechTeamZ; Valencia; A distancia; EUR 40.000 - 70.000; Jornada completa

Descripción de la vacante

A leading tech company is searching for a Mid-Senior level Digital Hardware ASIC Verification Engineer to join their exceptional team. This role involves developing and validating complex SoCs for next-gen digital IP, geographically available in Spain or Egypt. The candidate will be responsible for creating reusable testbenches and ensuring high-speed communications and signal processing excellence, collaborating closely with design engineers for continuous improvement.

Formación

• 5+ years ASIC verification experience required.
• Deep experience in SystemVerilog and UVM methodology.
• Familiarity with formal verification or coverage-driven techniques is a plus.

Responsabilidades

• Create verification plans and testbenches using SystemVerilog / UVM.
• Develop assertions, coverage models, and reusable components.
• Work closely with RTL designers and architects to resolve bugs.

Conocimientos

SystemVerilog

UVM methodology

Verification experience

Simulation tools

Scripting

Herramientas

VCS

Questa

Descripción del empleo

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Digital Hardware ASIC Verification Engineer (Spain / Egypt)

Work Location : Remote (Spain or Egypt) | Hybrid optional

Employment Type : Full-time Contractor via TechTeamz

Project Area : High-speed communications and signal processing chips

We're hiring a Verification Engineer to join a world-class team building next-gen digital IP. You’ll focus on creating reusable, scalable testbenches and validating complex SoCs using UVM methodology.

Responsibilities :

• Create verification plans and testbenches using SystemVerilog / UVM
• Develop assertions, coverage models, and reusable components
• Work closely with RTL designers and architects to resolve bugs
• Participate in regressions, reviews, and continuous improvement
• 5+ years ASIC verification experience
• Deep experience in SystemVerilog and UVM methodology
• Good knowledge of simulation tools (e.g., VCS, Questa) and scripting (Python, Perl)
• Familiarity with formal verification or coverage-driven techniques is a plus

If you are interested send over your CV.

Seniority level

• Seniority level Mid-Senior level

Employment type

• Employment type Full-time

Job function

• Industries Semiconductor Manufacturing

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