Design Verification Engineer

JR Spain; Torrejón de Ardoz; Híbrido; EUR 50.000 - 70.000; Jornada completa

Descripción de la vacante

A leading technology company is seeking an experienced Verification Engineer to work remotely from Spain or Egypt. You will focus on creating scalable testbenches for high-speed communications and signal processing chips using SystemVerilog and UVM methodology. The ideal candidate has over 5 years of ASIC verification experience and is proficient in simulation tools. This is a full-time contractor role offering hybrid work options.

Formación

• 5+ years ASIC verification experience.
• Deep experience in SystemVerilog and UVM methodology.
• Good knowledge of simulation tools and scripting.

Responsabilidades

• Create verification plans and testbenches using SystemVerilog/UVM.
• Develop assertions, coverage models, and reusable components.
• Work closely with RTL designers and architects to resolve bugs.

Conocimientos

SystemVerilog

UVM methodology

Python scripting

Perl scripting

VCS simulation tools

Questa simulation tools

Descripción del empleo

Client:

TechTeamz

Location:

Job Category:

Other

-

EU work permit required:

Yes

Job Reference:

9178647507314409472324610

Job Views:

1

Posted:

23.07.2025

Expiry Date:

06.09.2025

Job Description:

Digital Hardware ASIC Verification Engineer (Spain / Egypt)

Work Location: Remote (Spain or Egypt) | Hybrid optional

Employment Type: Full-time Contractor via TechTeamz

Project Area: High-speed communications and signal processing chips

We're hiring a Verification Engineer to join a world-class team building next-gen digital IP. You’ll focus on creating reusable, scalable testbenches and validating complex SoCs using UVM methodology.

Responsibilities:

• Create verification plans and testbenches using SystemVerilog/UVM
• Develop assertions, coverage models, and reusable components
• Work closely with RTL designers and architects to resolve bugs
• Participate in regressions, reviews, and continuous improvement
• 5+ years ASIC verification experience
• Deep experience in SystemVerilog and UVM methodology
• Good knowledge of simulation tools (e.g., VCS, Questa) and scripting (Python, Perl)
• Familiarity with formal verification or coverage-driven techniques is a plus

If you are interested send over your CV.

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