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Design Verification Engineer

JR Spain

Barcelona

A distancia

EUR 55.000 - 80.000

Jornada completa

Hace 12 días

Descripción de la vacante

A technology solutions provider is seeking a Digital Hardware ASIC Verification Engineer to join their team. This role involves creating reusable testbenches and validating complex SoCs using UVM methodology. Candidates should have over 5 years of ASIC verification experience and deep knowledge of SystemVerilog, UVM, and simulation tools. The position offers remote work flexibility from Spain or Egypt.

Formación

  • 5+ years ASIC verification experience.
  • Deep experience in SystemVerilog and UVM methodology.
  • Good knowledge of simulation tools (e.g., VCS, Questa) and scripting (Python, Perl).

Responsabilidades

  • Create verification plans and testbenches using SystemVerilog/UVM.
  • Develop assertions, coverage models, and reusable components.
  • Work closely with RTL designers and architects to resolve bugs.
  • Participate in regressions, reviews, and continuous improvement.

Conocimientos

SystemVerilog
UVM methodology
Python
Perl
VCS
Questa

Descripción del empleo

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Digital Hardware ASIC Verification Engineer (Spain / Egypt)

Work Location: Remote (Spain or Egypt) | Hybrid optional

Employment Type: Full-time Contractor via TechTeamz

Project Area: High-speed communications and signal processing chips

We're hiring a Verification Engineer to join a world-class team building next-gen digital IP. You’ll focus on creating reusable, scalable testbenches and validating complex SoCs using UVM methodology.

Responsibilities:

  • Create verification plans and testbenches using SystemVerilog/UVM
  • Develop assertions, coverage models, and reusable components
  • Work closely with RTL designers and architects to resolve bugs
  • Participate in regressions, reviews, and continuous improvement
  • 5+ years ASIC verification experience
  • Deep experience in SystemVerilog and UVM methodology
  • Good knowledge of simulation tools (e.g., VCS, Questa) and scripting (Python, Perl)
  • Familiarity with formal verification or coverage-driven techniques is a plus

If you are interested send over your CV.

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