DDR Design Engineer

Semidynamics; Barcelona; Hybrid; EUR 85,000 - 120,000; Full time

Benefits offered by this job

4 days per week in Barcelona office (城

WFH option

1 week remote worldwide

Job summary

Semidynamics is seeking a Senior Memory Design Engineer to design and develop memory subsystem solutions for our semiconductor portfolio. You will work within the Memory Design Team and closely with other teams to create efficient, high-performance memory subsystems that power modern designs.

The role requires +8 years industrial experience, knowledge of DDR/HBM, AXI protocol, and RTL design in Verilog/VHDL, with a focus on timing and basic block-level testing.

Qualifications

• Industrial experience +8 years.
• Knowledge of DDR or HBM memories. Proven experience in design and/or integration of memory controllers.
• Experience in AXI protocol.
• Proficiency in RTL design using Verilog or VHDL.
• Experience with Timing and Timings Constraints.
• Experience with basic block level testing.

Responsibilities

• Design and develop memory subsystem solutions for our semiconductor portfolio.
• Work within the Memory Design Team and collaborate with other teams to deliver high-performance memory subsystems.

Skills

DDR or HBM memories

AXI protocol

RTL design (Verilog/VHDL)

Timing constraints

Block-level testing

Education

Master or PhD

Tools

Python

Perl

Bash

TCL

Git

SVN

Job description

Are you passionate about microprocessor architecture? We need you! As a Senior Memory Design Engineer, you play a crucial role in designing and developing memory subsystem solutions for our semiconductor portfolio. You will work within the Memory Design Team and work closely with other teams' highly skilled engineers to create efficient and high-performance memory subsystems that are essential for modern designs.

Requirements

• Industrial experience +8 years
• Knowledge of DDR or HBM memories. Proven experience in design and/or integration of memory controllers.
• Experience in AXI protocol.
• Proficiency in RTL design using Verilog or VHDL
• Experience with Timing and Timings Constraints
• Experience with basic block level testing

Desired

• Master or PhD
• Knowledge of scripting languages (Python, Perl, Bash, TCL).
• Knowledge of revision control methodology and tools (git, svn).
• Knowledge of coherency concepts and protocols.
• Experience in memory map definition.

Why Semidynamics?

• Work at one of Europe's most promising deep-tech semiconductor scale-ups.
• Accelerated development path.
• 4 days per week in the Barcelona office (city center), 1 WFH.
• 1 week of work from everywhere in the world.
• Competitive package.
• A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.