Chief Digital Systems Architect

beBeeDigitalDesigner; España; Presencial; EUR 50.000 - 70.000; Jornada completa

Descripción de la vacante

A leading technology firm in Spain is seeking an experienced ASIC Design Engineer to lead the development of high-speed interface technologies. The ideal candidate will have over 5 years of experience in ASIC digital design, with strong skills in SystemVerilog and Verilog. This role emphasizes collaboration with cross-functional teams to design and implement advanced ASIC solutions.

Formación

• 5+ years of experience in ASIC digital design.
• Strong understanding of SoC microarchitecture, clocking, and reset strategies.
• Proficiency in SystemVerilog, Verilog, and simulation tools.
• Prior experience with high-speed memory or interface IP is a plus.

Responsabilidades

• Design end-to-end ASICs for digital IP, including memory interfaces and interconnects.
• Implement RTL code in Verilog / SystemVerilog.
• Collaborate with verification, physical design, and architecture teams.
• Drive synthesis, linting, CDC, and integration efforts.

Conocimientos

ASIC digital design

SystemVerilog

Verilog

simulation tools (ModelSim, Synopsys)

SoC microarchitecture

Herramientas

ModelSim

Synopsys

Descripción del empleo

We are seeking a seasoned ASIC Design Engineer to lead the development of cutting-edge high-speed interface technologies. This is an exciting opportunity for an experienced professional with a strong background in digital design, system integration, and RTL development.

The ideal candidate will have extensive knowledge of SoC microarchitecture, clocking, and reset strategies. They should be proficient in SystemVerilog, Verilog, and simulation tools such as ModelSim and Synopsys.

Key Responsibilities

• Design end-to-end ASICs for digital IP, including memory interfaces and interconnects
• Implement RTL code in Verilog / SystemVerilog
• Collaborate with verification, physical design, and architecture teams
• Drive synthesis, linting, CDC, and integration efforts

Requirements

5+ years of experience in ASIC digital design

Strong understanding of SoC microarchitecture, clocking, and reset strategies

Proficiency in SystemVerilog, Verilog, and simulation tools

Prior experience with high-speed memory or interface IP (e.g., PCIe, DDR, HBM) is a plus

This role offers a unique chance to work on challenging projects and contribute to the development of innovative technologies. If you are passionate about digital design and system integration, we encourage you to apply.