Analog Mixed Signal IC Design Engineer

JR Spain; Madrid; Presencial; EUR 60.000 - 100.000; Jornada completa

Descripción de la vacante

Join a cutting-edge organization as a Senior Analog Mixed-Signal IC Design Engineer in the vibrant heart of Madrid. This role offers the opportunity to work on innovative projects, defining requirements for complex components like ADCs and DACs, and utilizing advanced sub-nanometre CMOS technology. You will be responsible for designing and verifying mixed-signal systems, contributing to architectural concepts, and ensuring the highest standards in IC testing protocols. If you are passionate about pushing the boundaries of technology and eager to make a significant impact in the field, this position is tailor-made for you.

Formación

• Proven expertise in delivering full-custom analogue IP blocks.
• Experience with sub-nanometre CMOS technology.

Responsabilidades

• Define requirements for analogue and mixed-signal components.
• Carry out AMS design tasks including system design and layout.
• Plan and conduct characterisation tests.

Conocimientos

Analog IC Design

Mixed-Signal Design

CMOS Technology

Schematic Capture

Layout Verification

Testing Protocols

Educación

Bachelor's in Electrical Engineering

Master's in Analog Design

Herramientas

Cadence

SPICE

Descripción del empleo

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Analog Mixed Signal IC Design Engineer, madrid

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Client:

IC Resources

Location:

madrid, Spain

Job Category:

Other

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EU work permit required:

Yes

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Job Reference:

444624216449351680032460

Job Views:

8

Posted:

31.03.2025

Expiry Date:

15.05.2025

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Job Description:

I am recruiting a Senior Analog Mixed-Signal IC Design Engineer to join a cutting-edge organisation in the heart of Spain.

Responsibilities include, but are not limited to:

Defining the requirements for analogue and mixed-signal components such as ADCs, DACs, PLLs, data interfaces, and optoelectronics.

Carrying out AMS design tasks, including system design, schematic capture, layout, and verification using advanced sub-nanometre CMOS technology.

Establishing and reviewing layout guidelines.

Defining IC testing protocols and validating laboratory data.

Planning and conducting characterisation tests.

Creating models for analogue and mixed-signal components.

Integrating analogue subsystems into mixed-signal designs.

Exploring new architectural concepts and contributing to patent filings.

To be considered for this opportunity, you must have proven expertise in delivering full-custom analogue IP blocks in sub-nanometre CMOS technology.

Visa sponsorship is not available.

For more information, please contact Parm Shergill.