Verification Engineer

Chipright; Deutschland; Vor Ort; EUR 80.000 - 120.000; Vollzeit

Zusammenfassung

Chipright in Germany is seeking a Senior Digital Verification Engineer to drive digital verification across the chip. You will define test benches, implement UVM-based flows, and collaborate with the design team to achieve verification closure.

Expertise in SystemVerilog, OOP concepts, and scripting is required; knowledge of analog modeling and mixed-signal verification is a plus. The role emphasizes robust verification infrastructure and quality through automation.

Qualifikationen

• 3+ years of experience in ASIC/IC verification or design.
• Experience in UVM based verification flow.
• Good understanding of OOP concepts
• Familiar with scripting language like Makefile, Perl, Tcl or Python.
• Experience in SimVision or Verdi debug skills.
• Experience in Assertion and formal verification (Jasper, 0-in, IFV, Model checking) is a plus.

Aufgaben

• Define test bench infrastructure using SystemVerilog, UVM and Formal.
• Responsible for complete digital level verification.
• Modeling of analog functions in SystemVerilog.
• Responsible for complete chip level verification of mixed signal IC.
• Work closely with design team to architect a new design verification environment and produce high quality verification closure.
• Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.

Kenntnisse

UVM verification flow

Object oriented programming

SystemVerilog

Assertions & formal verification

Tools

SimVision

Verdi

Jobbeschreibung

Working as a Senior Digital Verification Engineer,you will:

• Define test bench infrastructure using SystemVerilog, UVM and Formal.
• Responsible for complete digital level verification.
• Modeling of analog functions in SystemVerilog.
• Responsible for complete chip level verification of mixed signal IC.
• Work closely with design team to architect a new design verification environment and produce high quality verification closure.
• Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.

What We Are Looking For?

• 3+ years of experience in ASIC/IC verification or design.
• Experience in UVM based verification flow.
• Good understanding of OOP concepts
• Familiar with scripting language like Makefile, Perl, Tcl or Python.
• Experience in SimVision or Verdi debug skills.
• Experience in Assertion and formal verification (Jasper, 0-in, IFV, Model checking) is a plus.