Trainee Program - Digital Accelerator IC Design (all genders)

Fraunhofer-Institut für Integrierte Schaltungen IIS; Erlangen; Vor Ort; EUR 23.000 - 32.000; Vollzeit

Zusammenfassung

Fraunhofer IIS in Erlangen invites applications for a Trainee Program in Digital IC Design. You will receive a comprehensive introduction to Digital IC Design under the guidance of experienced engineers and researchers, with hands-on work translating system specs into micro-architectures and RTL blocks.

The program is rooted in the Bavarian Chip Design Center (BCDC). You will learn SystemVerilog, accelerator design, RTL verification and system integration, while exploring trade-offs for power,

Qualifikationen

• Master’s degree in electrical engineering, computer engineering, computer science, or a related technical field.
• Knowledge of digital systems, computer architecture, programming and scripting.
• High motivation and ability to work independently.
• Strong teamwork and communication skills.
• Familiarity with HDL and experience with design tools such as Cadence or Synopsys is advantageous.
• English proficiency at B2/C1 level.

Aufgaben

• Introduction to Digital IC Design under guidance of experienced engineers.
• Hands-on experience translating specifications into micro-architectures and RTL blocks.
• Develop SystemVerilog skills and design accelerator components (datapaths, control logic, memory).
• Gain experience in accelerator design and RTL verification and integration.
• Explore architecture trade-offs for power, performance and area.
• Apply skills to research-oriented development of accelerators.
• Gain experience with industry-grade EDA tools.
• Build processor systems and hardware accelerators using RISC‑V.

Kenntnisse

Digital systems knowledge

Computer architecture

Programming and scripting

Motivation & independence

Team spirit & communication

HDL familiarity

EDA tools experience

English proficiency (B2/C1)

Ausbildung

Master's degree in electrical/computer engineering or related field

Tools

Cadence

Synopsys

Jobbeschreibung

Welcome to the Fraunhofer Institute for Integrated Circuits IIS!

As the largest institute within the Fraunhofer-Gesellschaft, we have been conducting research for over 30 years in diverse fields such as artificial intelligence, microelectronics, sensor systems, data acquisition, signal processing, and signal transmission. Talented individuals from various engineering and natural science disciplines will find a wide range of exciting research topics under one roof. A few highlights that reflect our innovative strength include neuromorphic computing, 5G/6G mobile communication technologies, generative AI in speech and signal processing, and X-ray imaging for e-mobility. And that’s just the beginning!

Are you passionate about microelectronics and ready to launch your career in Digital IC Design? Join our Trainee Program and become part of a growing high-tech ecosystem that’s driving innovation in chip development.

Here’s how you will make a difference

The program is rooted in the Bavarian Chip Design Center (BCDC), a strategic initiative supported by the Free State of Bavaria. BCDC aims to strengthen the regional semiconductor industry and develop skilled talent in integrated circuit (IC) design. With the increasing demand for chip designers in Europe, especially in Bavaria, there has never been a better time to join this future oriented field.

• Introduction to Digital IC Design: You will receive a comprehensive introduction to Digital IC Design under the guidance of experienced engineers and researchers.
• Practical Design Experience: You will gain hands‑on experience in translating system and functional specifications into micro‑architectures and implementing digital hardware blocks in RTL.
• SystemVerilog and RTL Design: You will develop practical skills in SystemVerilog and learn to design key accelerator components such as datapaths, control logic, and memory subsystems.
• Accelerator Design and Optimization: You will gain hands‑on experience in neural‑network accelerator architecture, RTL verification and system integration, while exploring architectural and implementation trade‑offs for optimized power, performance, and area (PPA).
• Research-Oriented Development: You will apply your skills to an integrated accelerator and explore architectural trade‑offs and optimization opportunities.
• Experience with EDA Tools: You will gain hands‑on experience with industry‑grade EDA tools.
• Knowledge of SystemVerilog: You will become familiar with SystemVerilog and learn how to build processor systems and hardware accelerators using the RISC‑V architecture.
• Professional Preparation: You will build a strong foundation for a career in digital IC design and hardware accelerator development.

What you bring to the table

• Master's degree in electrical engineering, computer engineering, computer science, or a related technical field.
• Knowledgeof digital systems, computer architecture, programming, and scripting.
• High level ofmotivationand the ability towork independently.
• Strongteam spiritand good communication skills.
• Abackground in studiesfocused on digital hardware, computer architecture, embedded systems, or hardware acceleration is desirable, but not mandatory.
• Familiaritywith a hardware description language (HDL) is preferred.
• Experiencewith design tools such as Cadence or Synopsys is considered advantageous.
• Proficiency inEnglishat least atB2/C1 level.

What you can expect

• Theoretical Experience: You will gain expertise in digital IC and hardware accelerator design, from microarchitecture and RTL to verification and low‑power PPA optimization.
• Practical Training: We will guide you in translating theoretical concepts into practical hardware designs and developing critical thinking to evaluate real‑world design trade‑offs.
• Supportive Environment: We take your goals and needs seriously by providing consistent guidance and support through assigned mentors and regular feedback sessions to enhance your experience.
• Work-Life Balance: Enjoy a healthy work-life balance with flexible working hours.
• Unique Opportunities: We offer you access to a unique network of experts and partners in research and industry, insights into innovative technologies and state‑of‑the‑art design methodologies.
• R&D Experience: Get a glimpse into one of Europe’s leading R&D IC design facilities.
• Professional Growth: Enjoy valuable work experience at Fraunhofer, Europe’s largest organization for applied research and a top-rated employer.

The position is initially limited to 6 months, starting in April 2027. The weekly working time is 39 hours. Appointment, remuneration and social security benefits based on the public‑sector collective wage agreement (TVöD).

We value and promote the diversity of our employees' skills and therefore welcome all applications - regardless of age, gender, nationality, ethnic and social origin, religion, ideology, disability, sexual orientation and identity.

About Fraunhofer

The Fraunhofer-Gesellschaft currently operates 74 institutes and research institutions throughout Germany and is the world’s leading applied research organization. Around 30 000 employees work with an annual research budget of 3.4 billion euros. The Fraunhofer Institute for Integrated Circuits IIS, located in Erlangen, is the largest institute of the Fraunhofer-Gesellschaft with more than 1 200 employees.

With its focus on developing key technologies that are vital for the future and enabling the commercial utilization of this work by business and industry, Fraunhofer plays a central role in the innovation process. As a pioneer and catalyst for groundbreaking developments and scientific excellence, Fraunhofer helps shape society now and in the future.