STA Engineer (M, F, D)

Apple; München; Vor Ort; EUR 60.000 - 80.000; Vollzeit

Zusammenfassung

Apple in München is seeking talented engineers to join the STA team. You will develop automated signoff flows and work closely with integration teams on high-quality timing and noise convergence for full chip designs.

The ideal candidate will hold a MSEE, possess strong experience in static timing analysis, and be fluent in English. Apple promotes accessibility and inclusion, ensuring a diverse workplace where everyone feels they belong.

Qualifikationen

• Strong experience in Static Timing analysis.
• Extensive experience with a commercial STA tool.
• Ability to fluently speak and write in English.

Aufgaben

• Develop automated block and full chip level signoff flows.
• Conduct full chip Timing/Noise convergence and signoff.
• Enable hierarchical Timing flows.
• Perform power optimizations.
• Generate block level budget for correlation with Full Chip.

Kenntnisse

Static Timing analysis

Commercial STA tools

Fluent in English

Hierarchical design approach

Backend STA closure

Communication skills

Ausbildung

MSEE or equivalent

Jobbeschreibung

Summary

We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.

Description

You will be responsible for:

• Developing automated block and full chip level signoff flows
• Full Chip Timing/Noise convergence and full signoff for high quality TO
• Enabling hierarchical Timing flows
• Power optimizations
• Generating block level budget and context for correlation with Full Chip
• Driving custom IP integration and custom timing checks flows
• Closing work with Design, DFT, architecture and Power team

Minimum Qualifications

• You hold a MSEE or equivalent strong experience in Static Timing analysis
• Extensive experience with one of the commercial STA tools
• Ability to fluently speak and write in English

Preferred Qualifications

• Familiarity with hierarchical design approach, top-down design, timing and physical convergence
• Experience with backend STA closure and Signoff
• Deep understanding of designs' constraints development
• Good understanding of AC timing from specs to implementation
• Good understanding of DFT modes and their constraints
• Good communication skills and team player
• Quick learning of flows and methods
• Advantage - Understanding noise and signal integrity effects
• Advantage - Timing margins fundamental from synthesis to signoff
• Advantage - Experience with scripting

Additional information

At Apple, we’re not all the same. And that’s our greatest strength. We draw on the differences in who we are, what we’ve experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. We are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace.

Role Number: 200653786-1731