STA Lead (m/f/d)

Apple; München; Vor Ort; EUR 120.000 - 160.000; Vollzeit

Zusammenfassung

Apple is seeking a Lead of a local Timing team responsible for all aspects of SoC timing in terms of timing and synthesis. You will be responsible for timing sign-off, STA and sign-off flow development, ownership of full chip, IP, and block level timing constraints for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints.

You will also collaborate with RTL designers to understand design intent and clock structure, with CAD to develop

Qualifikationen

• Experience in writing ASIC timing constraints and timing closure.
• Experience with STA tools (Primetime) and flow, knowledge of timing corners/modes.
• Hands-on experience in timing/SDC constraints generation and management.
• Proficiency in scripting languages Tcl and Perl.
• Knowledge of synthesis, DFT and backend-related methodology/tools.
• Excellent communication and collaboration across diverse teams.
• Ability to work in an international team under strict deadlines.
• Experience managing technical teams in ASIC design.
• Proficiency in English.

Aufgaben

• Lead timing sign-off and STA flow development.
• Own full-chip, IP, and block-level timing constraints.
• Collaborate with RTL, CAD, and Physical Design teams to close timing.
• Develop ideas to verify timing constraints and improve flows.
• Ensure timely delivery of collaterals with high quality.

Kenntnisse

Timing constraints engineering

Project/team leadership

Cross-functional collaboration

English proficiency

SDC/flow knowledge

Ausbildung

Bachelor's/Master's Degree in Electrical Engineering

Tools

Primetime

Tcl

Perl

Jobbeschreibung

Summary

Why Apple? We live in a mobile and device-driven world where knowledge of the physical world around us is needed. We rely on this knowledge to get around, to learn about our environment and to enable spectacular new features for custom applications. Apple is meeting those needs as robustly and as creatively as possible and is interested in people who want to help meet that commitment. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. If that sounds like the kind of environment that you find intriguing, then let's talk.

Description

As a Lead of a local Timing team, you will be responsible for all aspects of SoC design in terms of timing and synthesis. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will also closely collaborate with RTL designers to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical Design team to close and sign-off timing. You will come up with ideas and plans to verify timing constraints, innovate timing constraints and flow to facilitate timing closure, improve synthesis result, improve methodologies and ensure that your team delivers the required collaterals in time with high quality.

Minimum Qualifications

• Relevant years of experience in writing ASIC timing constraints and timing closure.
• Validated experiences in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations & signal integrity related issues.
• Hands-on experiences in timing/SDC constraints generation and management.
• Proficient in scripting languages (Tcl and Perl).
• Have good knowledge in synthesis, DFT and backend-related methodology and tools.
• Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams.
• Ability to work well in an international team, take responsibility, perform under strict deadlines and motivate self to balance priorities.
• Relevant experience in managing technical teams, ideally in the area of ASIC design.
• Proficiency in English language is required.

Preferred Qualifications

• Bachelor's/Master's Degree in Electric Engineering with relevant experience.

Apple is an Equal Opportunity Employer committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, and individuals with disabilities. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.

At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

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