Sr. Engineer, Digital Design Munich, Bavaria, Germany

SiTime Corp.; München; On-site; EUR 90,000 - 120,000; Full time

Job summary

SiTime Corp. is seeking a Senior Logic Design Engineer to advance MEMS-based timing solutions. You will develop RTL designs, write testbenches, and verify with SystemVerilog assertions, while collaborating across analog, verification, backend, system and test teams.

Strong English communication and a background in digital logic are essential. Responsibilities include timing constraints, synthesis, and post-Si debugging, with opportunities to influence design tradeoffs and performance.

Qualifications

• Master’s degree in electrical engineering plus 5 years of relevant work experience.
• Excellent verbal and written communication skills in English.
• Proficient in Verilog and SystemVerilog.
• Expertise in digital logic design fundamentals (clock dividers, multi-clock logic, CDC, FIFO, FSM).
• Skilled in RTL design, synthesis, timing constraints and STA.
• Scripting languages Perl/Tcl/Python.

Responsibilities

• Develop micro-architecture specifications from PRD.
• Create RTL design using Verilog/SystemVerilog.
• Develop standalone test benches to verify RTL behavior.
• Write and verify SystemVerilog Assertions (SVA).
• Write timing constraints and clock definitions for synthesis/place-and-route.
• Run industry-standard synthesis tools (Genus, Design Compiler) and fix timing issues.
• Analyze timing/area/power tradeoffs and optimize.
• Review STA reports (PrimeTime) and address issues.
• Collaborate with analog, verification, backend, system and test teams.
• Post-Si bring-up, validation and debugging.

Skills

Verilog

SystemVerilog

English communication

Perl scripting

Python scripting

Tcl scripting

Education

Master's degree in Electrical Engineering

Ph.D. in Electrical/Computer Engineering

Tools

Genus

Design Compiler

Primetime

Job description

Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and humanoid robots, wearables and IoT.

Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power, and better reliability. With more than 4 billion devices shipped, SiTime is changing the timing industry. For more information, visit: www.sitime.com .

Job Summary

We at SiTime take pride in being the only company in the market that offers MEMS-based timing solutions. Our MEMS dies are uniquely complemented by our CMOS dies in the same package. We use state-of-the-art analog and digital circuits to achieve very aggressive design specs for our timing solutions. Our precision timing products keep pushing the boundaries of the industry across all dimensions and are by far superior to our competition. This has enabled us to continuously gain market share.

This has been achieved by pushing the innovation boundaries in MEMS and CMOS. Consisting of analog and digital blocks, our CMOS dies present unique technical challenges. The digital portion of our chips has been growing in the past few years and is expected to grow more rapidly in the upcoming years as our functionality and features scale up. To address our unique technical challenges, we are looking for a strong Senior Logic Design Engineer with a solid background in key digital design and implementation areas. It is not necessary to meet all job requirements to be a qualified candidate for the position.

Responsibilities:

• Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD).
• Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL.
• Developing standalone test benches to verify the RTL behavior.
• Writing and verifying SystemVerilog Assertions (SVA) for a design.
• Writing timing constraints and clock definition for synthesis and place and route tools.
• Running industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix timing problems if they arise.
• Understanding various design tradeoffs including timing/area/power and knowing how to improve them.
• Reading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time).
• Cross-functional interactions and communication with various teams within SiTime including analog, verification, backend, system, and test engineering teams.
• Post-Si bring-up, validation, and debugging.

Qualifications & Requirements:

• Master’s degree in electrical engineering plus 5 years of relevant work experience in the industry.
• Excellent verbal and written communication skills in English.
• Proficient in Verilog and SystemVerilog.
• Expertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etc.
• Basic understanding of Discrete time Signal Processing theory, FIR, and IIR filter design.
• Solid experience in digital design flow including RTL design, synthesis, timing constraints, and STA.
• Skilled in scripting languages Perl/Tcl/Python.

Desired Characteristics & Attributes:

• Ph.D. in electrical/computer engineering plus 3 years of relevant industry experience.
• 2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing.
• 2-5 years of experience in designing Digital Phase-Locked Loops (DPLL).
• Experience in complex FSM design.
• Familiarity with MATLAB, Simulink, or any other high-level modeling tools.
• Basic understanding of the Control Theory.

Compensation:

At SiTime, we believe great work deserves great rewards. We offer a comprehensive and highly competitive compensation package designed to attract top talent.

In addition to base salary, this role is eligible for a quarterly bonus tied to the achievement of innovation goals—reflecting our commitment to recognizing meaningful impact. We also offer equity grants, providing a meaningful opportunity to share in the company’s future growth and success.

SiTime is committed to providing equal employment opportunities to all employees and applicants. Employment decisions are based on qualifications, merit, and business needs. We do not discriminate on the basis of any characteristic protected by applicable law.

Learn More about SiTime:

Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique.