Senior Digital Design Engineer - (Visa Sponsorship Supported)

European Tech Recruit; Köln; Vor Ort; EUR 60.000 - 80.000; Vollzeit

Zusammenfassung

A leading semiconductor company in Germany seeks an experienced Digital Design Engineer to contribute to the development of high-performance digital ICs. Candidates should have strong expertise in RTL design, backend implementation, and modern process nodes, along with a relevant educational background. This role offers a competitive salary in an innovative environment.

Qualifikationen

• 3–5 years of relevant experience for mid-level positions.
• 6+ years of experience with ownership of IP/SoC for senior-level positions.
• Strong proficiency in RTL design using SystemVerilog/VHDL.

Aufgaben

• Own RTL design and micro-architecture of digital subsystems.
• Develop and optimize backend flow including timing closure and signoff.
• Support integration of digital blocks with analog mixed-signal subsystems.

Kenntnisse

RTL design

Digital verification

Scripting (Python, Tcl)

Low-power design techniques

Problem-solving skills

Ausbildung

MSc or PhD in Electrical Engineering or related field

Tools

Cadence

Synopsys

Mentor

Jobbeschreibung

Overview

Digital Design Engineer

A fantastic opportunity for an experienced Digital Design Engineer to join an award-winning semiconductor company whose main product is a break-through and patented wide band width transceiver“ microchip for application in e.g. ultrafast 5G-A and 6G wireless infrastructure equipment and devices.

About the Role

We are looking for Digital Design Engineers with strong expertise in either frontend RTL design, backend physical implementation, or ideally both. You will contribute to the development of high-performance digital and mixed-signal ICs in advanced technology nodes such as 22FDX and other FinFET / FD-SOI processes.

Responsibilities

• Own RTL design and micro-architecture of digital subsystems (e.g., DSP blocks, control logic, interfaces).
• Develop and optimize backend flow, including synthesis, floorplanning, placement and routing (P&R), timing closure, and signoff (STA, LVS, DRC).
• Perform logic synthesis and work with physical design teams to ensure a clean handoff and alignment across digital and mixed-signal boundaries.
• Support integration of digital blocks with analog / mixed-signal subsystems.
• Generate documentation, testbenches, and support post-silicon bring-up and debugging.

Your Profile

• Strong proficiency in RTL design using SystemVerilog / VHDL, digital verification, and scripting (Python, Tcl, etc.).
• Experience with EDA tools from Cadence, Synopsys or Mentor for logic synthesis, static timing analysis, and backend implementation.
• Familiarity with low-power design techniques, clock domain crossing (CDC), and hierarchical SoC design.
• Hands-on experience in physical implementation (floorplanning, P&R, CTS, STA, DRC, LVS).
• Experience with modern process nodes, especially 22FDX, 16 / 12nm FinFET, or similar. Good understanding of mixed-signal integration, top-level assembly, and testability concepts (DFT is a plus).
• Strong problem-solving skills, attention to detail, and ability to work independently.

Qualifications

• Mid-Level : 3–5 years of relevant experience in digital IC design.
• Senior-Level : 6+ years, with ownership of IP / SoC blocks or backend flows.
• MSc or PhD in Electrical Engineering, Microelectronics, or related field

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