QPU Integration Engineer (Assembly & Characterization focused) (f/m/d)

Entangled Future; Hamburg; Hybrid; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Competitive salary

Flexible hours

Team events

Professional development

Wellness benefits

Bike leasing

Moving benefits

At the forefront of technology

Modern workplace

Job summary

eleQtron in Hamburg is seeking a Senior QPU Integration Engineer (Assembly & Characterization focused) to lead post-fabrication packaging and end-to-end testing of quantum processor architectures. You will bridge chip design and cleanroom execution, owning packaging modules and characterization test flows.

You will collaborate with QPU designers, fab partners, and test teams, drive DFA/DFT guidelines, and manage internal and external projects, delivering high-yield packaging solutions for

Qualifications

• Master’s or Ph.D. in Microelectronics, Electrical Engineering, Materials Science, Mechanical Engineering, Applied Physics, Nanotechnology, or related field.
• 5+ years hands-on experience in microelectronics assembly, advanced semiconductor packaging, or chip characterization in a cleanroom (ISO 4–5).
• Deep technical expertise in post-fab assembly techniques (flip-chip bonding, wire bonding, die attach, substrates/interposers).
• Extensive experience in using structural, optical, and electrical characterization protocols (wafer probing, SEM, optical profilometry, defect mapping).
• Experience managing joint development projects with external packaging foundries or OSATs.

Responsibilities

• Serve as SME for advanced chip assembly and back-end packaging processes.
• Develop and optimize high-yield packaging flows for fragile quantum hardware.
• Define, standardize, and execute multi-scale characterization protocols (wafer-level to post-packaging).
• Feed metrology data and defect density mapping into process/design iterations.
• Collaborate with QPU designers and fab specialists to set DFA/DFT guidelines.
• Translate chip architectures into assembly tolerance stacks and pinout specs.
• Lead internal cleanroom assembly and test workflows and schedule runs.
• Oversee R&D projects to qualify novel packaging materials and inspection techniques.
• Drive project management and technology transfer with external packaging foundries and OSATs.

Skills

Microelectronics assembly

Semiconductor packaging

Chip characterization

DOE / SPC

Python / Pandas

Team leadership

English proficiency

Education

Master’s or Ph.D. in Microelectronics / Electrical Engineering / Materials Science

Tools

Automated wafer probers

SEM

Cryogenic characterization setups

Job description

QPU Integration Engineer (Assembly & Characterization focused) (f/m/d) at eleQtron, Hamburg, Hamburg, Germany. A mid-level full time position in the Chip design & Packaging team, listed under hardware engineering.

We are looking for a Senior QPU Integration Engineer (Assembly & Characterization focused).You will be a lead technical expert in our QPU Development team, driving the post-fabrication physical integration, advanced packaging, and end-to-end characterization of next-generation quantum processor architectures. In this pivotal role, you will serve as the primary bridge between chip design teams and cleanroom execution. You will own chip-level packaging, assembly modules, and characterization test flows, leading R&D activities within our internal cleanroom facility while managing strategic assembly and testing projects with external foundry and packaging partners.

What you can expect from eleQtron

• Competitive salary: We value our team members and therefore provide remunerations that reflect this, additionally rewarding achievements.
• Flexible working hours : We offer personal freedom through a variety of flexible work schedules
• Team spirit: In our international and diverse team, and with our regular team events, having fun at work is simply part of the culture
• Further development: We want to grow together and so we offer our team members needs-based, individualized further training as well as plenty of room for personal development
• Wellness Package : We offer health-promoting benefits such as fitness programs like UrbanSportsClub to support your well-being
• Bike Leasing: Stay Mobile and Sustainable with Our Company Bike Leasing Program
• Moving Benefits: A warm welcome! We are happy to support employees who move for us with a bonus
• At the forefront : Work at the forefront of technology, where academic research meets commercial applications
• Modern workplace: We have a high-quality infrastructure with laboratory space, offices and meeting rooms

Responsibilities

• Serve as the Subject Matter Expert (SME) for advanced chip assembly and back-end packaging processes (e.g., precision dicing, flip-chip bonding, wire bonding, 3D interconnects, substrate integration, and cryogenic packaging stacks).
• Develop and optimize robust, high-yield packaging flows for fragile, high-value quantum hardware while minimizing mechanical, thermal, and electrostatic stress.
• Define, standardize, and execute multi-scale characterization protocols across wafer-level, die-level, and post-packaging stages (e.g., physical inspection, electrical probing, optical/metrology mapping, and cryogenic pre-screening).
• Feed metrology data, yield metrics, and structural/electrical defect density mapping back into process and design iterations.
• Collaborate closely with QPU designers, thermal/RF modeling engineers, and fab specialists to establish design-for-assembly (DFA) and design-for-testability (DFT) guidelines.
• Translate chip architectures into actionable assembly tolerance stacks, wire-bonding maps, and pinout/interconnect specs
• Take the lead in managing daily internal cleanroom assembly and test workflows, scheduling runs, setting baseline packaging procedures, and resolving real-time hardware deviations
• Oversee internal R&D projects to qualify novel packaging materials, interconnect schemes, and non-destructive inspection/testing techniques.
• Drive project management and technology transfer with external commercial packaging foundries, assembly OSATs, and research partners.
• Manage out-of-house assembly lines, wafer-to-wire-bond delivery schedules, yield matching, and subcontractor deliverables.

Requirements

• Master’s or Ph.D. in Microelectronics, Electrical Engineering, Materials Science, Mechanical Engineering, Applied Physics, Nanotechnology, or a related field.
• 5+ years (or equivalent extensive industry experience) of hands-on experience in microelectronics assembly, advanced semiconductor packaging, or chip characterization within a cleanroom environment (Class 10 / 100 / ISO 4–5).
• Deep technical expertise in post-fab assembly techniques (e.g., flip-chip bonding, thermocompression/ultrasonic wire bonding, precision die attach, substrates/interposers, and encapsulation).
• Extensive experience in executing structural, optical, and electrical characterization protocols (e.g., automated wafer probing, SEM, optical profilometry, shear/pull testing, and defect mapping).
• Demonstrated track record of managing joint development projects (JDPs) or technology transfers with external packaging foundries, OSATs, or characterization labs.
• Strong project management capabilities, including timeline management, risk mitigation, and tracking vendor deliverables.
• Solid understanding of Statistical Process Control (SPC), Design of Experiments (DOE), PFMEA, and structured RCA techniques (e.g., 8D, 5-Whys, Fishbone).
• Proficiency in scripting and data processing tools (e.g., Python using Pandas/NumPy, MATLAB, or SQL) for multi-chip yield extraction, automated analysis, and visual dashboarding.
• Strong leadership capabilities with a track record of bridging communication gaps between multi-disciplinary design, fab, assembly, and testing teams.
• Fluent in English (written and spoken) with excellent technical writing and presentation skills.

Nice to Have

• Experience in quantum hardware packaging (e.g., low-loss superconducting interconnects, 3D integration/TSVs, or high-density cryogenic wiring/PCB interfaces).
• Hands-on experience with automated wafer probers, high-throughput inspection tools, or cryogenic characterization setups.
• Proven experience establishing assembly inspection lines or setting up cleanroom packaging tools from scratch.
• Background in managing external vendor contracts, assembly IP, and wafer-to-module.