Principal Verification Engineer

microTECH Global Ltd; München; Vor Ort; EUR 70.000 - 90.000; Vollzeit

Zusammenfassung

A technology solutions company in Munich is seeking a Principal Digital Verification Engineer. The role involves leading design verification efforts, ensuring compliance with functional safety, and collaborating with cross-functional teams. Candidates should have over 8 years of experience and proficiency in hardware description languages, along with experience in using CADENCE tools. Competitive compensation and opportunities for professional growth are offered.

Qualifikationen

• 8+ years of experience in design verification.
• Experience leading verification teams.
• Proficiency in hardware description languages.

Aufgaben

• Collaborate with Design and Verification teams for Design Verification.
• Ensure compliance with ISO standards in development.
• Work with safety and project managers on functional safety deliverables.

Kenntnisse

Design Verification

Functional Safety

Verilog

VHDL

SystemC

SystemVerilog

CADENCE tools

Ausbildung

Degree in Electrical Engineering or Computer Science

Tools

Xcelium

VManager

Specman / e

JasperGold

Jobbeschreibung

Job Title: Principal Digital Verification Engineer

Job Type: Permanent

Location: Munich, Germany

Start: ASAP

Our client is a “solution SoC” company with rich experience in different markets leading innovations with customers around the world.

In the fields of "automotive", "data centre & networking", and "smart devices", functionality and performance are becoming increasingly sophisticated; they design and develop their products based on common concepts, including subsystem configuration and bus architecture, and deliver SoCs that meet their scalability needs and enable the optimal function and performance for each application.

Responsibilities

• You work with engineers of the Design Team and Verification Team to carry out Design Verification (SpecmanE, UVM)
• You proceed with development (design and verification) in compliance with ISO (Functional Safety)
• You work with safety manager, project manager and development team on functional safety work products.

Profile

• You have a degree in electrical engineering, computer science or similar.
• You have solid experience (8+ years) in the area of design verification.
• You have led the verification team performing verification tasks according to the functional safety processes.
• You are not only proficient in hardware description languages (Verilog, VHDL, SystemC, SystemVerilog), but bring extensive experience across the entire SoC design flow.
• You have experience in functional safety and in the use of relevant tools and methods.
• You have experience with CADENCE tools for Functional Verification like Xcelium, VManager, Specman / e and JasperGold.