Principal Engineer System Compute (f/m/div)

Infineon Technologies AG; Langen; On-site; EUR 80,000 - 110,000; Full time

Job summary

Infineon Technologies AG in Langen, Germany is looking for a Principal Engineer System Compute to define compute architectures for automotive MCUs/MPUs. This role emphasizes leading HW/SW co-design for performance and determinism, alongside driving memory and interconnect strategies.

Ideal candidates will possess a Master’s degree in relevant fields, have at least 6 years of CPU/DSP/NPU architecture experience, and exhibit strong leadership and technical skills in real-time systems. Fluency in English is required; German is a plus.

Qualifications

• A master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• At least 6 years in CPU/DSP/NPU architecture/microarchitecture for embedded/edge SoCs.
• Strong parallel compute expertise and understanding of memory systems/interconnects.

Responsibilities

• Define compute subsystem architecture for automotive MCUs/MPUs.
• Lead HW/SW co‑design with compiler, runtime, and ML teams.
• Provide technical leadership across development flow.

Skills

CPU/DSP/NPU architecture

Parallel compute expertise

Hands-on capability with modeling/tools

Great architecture specification skills

Fluent English skills

Education

Master’s degree in Electrical Engineering

Tools

Python

C/C++

Job description

Your Role

As a Principal Engineer System Compute, you will define compute architectures for automotive MCUs/MPUs and lead HW/SW co-design to achieve high performance and determinism. You will drive memory and interconnect strategy, performance modeling and optimization, and provide technical leadership across the development lifecycle.

Key Responsibilities

• Define compute subsystem architecture for automotive MCUs/MPUs: CPU cores, DSP/vector, and AI accelerators
• Translate system requirements into specs and PPA/latency/determinism targets; drive architectural trade‑offs
• Lead HW/SW co‑design with compiler, runtime, firmware, and ML teams to optimize kernels and data movement
• Architect memory hierarchy, DMA, interconnect/coherency, and QoS to meet real‑time deadlines
• Build/guide performance modeling and workload characterization (control, audio, vision, edge inference)
• Provide technical leadership across development flow: design reviews, mentoring, roadmap/IP strategy, customer/partner

Your Profile

Qualifications and skills to help you succeed

• A master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (advanced degree preferred for this level)
• At least 6 years in CPU/DSP/NPU architecture/microarchitecture for embedded/edge SoCs; principal‑level leadership
• Strong parallel compute expertise (SIMD/vector, multi‑core scaling, accelerator integration) and deep understanding of memory systems/interconnects (cache/scratchpad, DMA, coherency, NoC, QoS)
• Hands‑on capability with modeling/tools (e.g., Python, C/C++, spreadsheets/analytical models, perf simulators, trace tooling); ability to define new methodologies when needed
• Familiarity with real‑time determinism plus safety/security requirements (isolation, ECC, functional safety concepts)
• Great architecture specification, stakeholder alignment, and mentoring skills
• Fluent English skills, German is a plus

Contact

Guilherme Soares

EEO & Diversity

We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills.