Principal Engineer System Compute (f/m/div)

Infineon Technologies; Frankfurt; On-site; EUR 80,000 - 110,000; Full time

Job summary

Infineon Technologies is seeking a Principal Engineer System Compute for their R&D team in Frankfurt, Germany. This role involves defining compute architectures for automotive MCUs and leading HW/SW co-design efforts. Candidates should have a master’s degree in a relevant field, at least 6 years of experience in CPU/DSP architecture, and strong modeling skills. Fluency in English is required, while German is a plus. The company values diversity and inclusion in their hiring process.

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field required.
• At least 6 years of experience in CPU/DSP/NPU architecture/microarchitecture.
• Hands-on capability with modeling/tools like Python, C/C++.

Responsibilities

• Define compute architectures for automotive MCUs/MPUs.
• Lead HW/SW co-design with various teams.
• Architect memory hierarchy and meet real-time deadlines.

Skills

CPU/DSP/NPU architecture

Embedded/edge SoCs experience

Parallel compute expertise

Modeling/tools capabilities

Real-time determinism

English fluency

German language skills

Education

Master’s Degree in Electrical Engineering

Master’s Degree in Computer Engineering

Master’s Degree in Computer Science

Tools

Python

C/C++

Job description

#WeAreIn for jobs that impact everyone's life. What if your ideas could change the way the world connects, powers up, or thinks? As a Principal Engineer System Compute on our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Are you in?

Your Role

• Define compute architectures for automotive MCUs/MPUs: CPU cores, DSP/vector, and AI accelerators
• Translate system requirements into specs and PPA/latency/determinism targets; drive architectural trade-offs
• Lead HW/SW co-design with compiler, runtime, firmware, and ML teams to optimize kernels and data movement
• Architect memory hierarchy, DMA, interconnect/coherency, and QoS to meet real-time deadlines
• Build/guide performance modeling and workload characterization (control, audio, vision, edge inference)
• Provide technical leadership across development flow: design reviews, mentoring, roadmap/IP strategy

Your Profile

Qualifications And Skills To Help You Succeed

• A master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (advanced degree preferred for this level)
• At least 6 years in CPU/DSP/NPU architecture/microarchitecture for embedded/edge SoCs; principal-level leadership
• Strong parallel compute expertise (SIMD/vector, multi-core scaling, accelerator integration) and deep understanding of memory systems/interconnects (cache/scratchpad, DMA, coherency, NoC, QoS)
• Hands-on capability with modeling/tools (e.g., Python, C/C++, spreadsheets/analytical models, perf simulators, trace tooling); ability to define new methodologies when needed
• Familiarity with real-time determinism plus safety/security requirements (isolation, ECC, functional safety concepts)
• Great architecture specification, stakeholder alignment, and mentoring skills
• Fluent English skills, German is a plus

We are an equal opportunity employer. Infineon embraces diversity and inclusion and welcomes everyone for who they are. We base our recruiting decisions on the applicant’s experience and skills. Learn more about our diverse contact channels.