Layout Engineering Intern m/f/d

118-WW TMG MFG OPS; Freising; Vor Ort; EUR 11.000 - 17.000; Teilzeit

Benefits dieser Stelle

Attractive compensation

International work environment

Professional development opportunities

Zusammenfassung

Texas Instruments in Freising, Germany, is offering a Layout Engineering Intern position to join a design team working on mixed-signal IC layouts for DC/DC converters and controller solutions across automotive, industrial, and consumer markets.

You will contribute to block-level layout, floor planning, and parasitic extraction while collaborating with cross-functional teams and participating in reviews. Final-year Electrical Engineering students who can provide transcripts are invited to apply.

Qualifikationen

• Final-year student (Bachelor or Master) in Electrical Engineering or equivalent.
• Submit latest transcript of grades with application.

Aufgaben

• Layout IC at block level, perform floor planning and area estimation.
• Design power transistor and lead frame for modules and discrete devices.
• Die and package-board parasitic extraction.
• Physical verification and post-layout analysis (DRC, LVS, EM, ESD).
• Use tools to automate basic layout tasks, floor planning and area estimations.
• Collaborate with analog/digital design and cross-functional teams.
• Participate in layout design reviews and automation/verification development.

Kenntnisse

IC layout

Teamwork

Time management

English proficiency

Ausbildung

Electrical Engineering (BSc/MSc)

Tools

Cadence Virtuoso

Unix

Jobbeschreibung

Change the world. Love your job.

Texas Instruments is seeking askilled, enthusiastic Layout Engineering Internto join our design team in Freising , Germany. In this role you and your team will work on layout design of Mixed Signal Integrated Circuits (ICs). In your work you will have the opportunity to work as part of experienced mixed signal team developing next generation DC/DC converter, stand alone power stage and controller solutions for personal electronics, industrial, automotive and data centre markets.

Job duties of Layout Engineering Intern will include:

• Block level IC layout, top level integration, floor planning, and area estimation
• Power transistor and package lead frame design for discrete and module devices
• Die and package-board parasitic extraction
• Physical verification and post-layout analysis (DRC, LVS, EM, ESD)
• Use advanced tools to automate basic block level layout tasks, floor planning, and area estimations.

Your additional responsibilities will also include, but will not be limited to:

• Collaborating with analog/Digital design, and other cross functional teams such as product engineers, program managers, systems etc...
• Participating in layout design reviews
• Design flow automation/verification function development

Minimum requirements:

• Qualified candidates are in their final years of their ongoing studies (master or bachelor) within Electrical Engineering or equivalent
• Please add your latest transcript of grades to your application

Preferred qualifications:

• Good understanding of analog electronics theory and device physics.
• Experience of Cadence Virtuoso or equivalent IC layout design tools
• Ability to work in teams and collaborate effectively with people in different functions
• Ability to take the initiative and drive for results
• Strong time management skills that enable on-time project delivery
• Strong analog problem solving skills, IC Layout design experience and knowledge of switching DCDC regulators is a plus
• Unix and Cadence database management skills
• Strong verbal and written communication skills in English, German is a plus
• Shell or other programming language is a plus

Our Offer for you:

• Benefit from an attractive compensation
• Join an international work environment where your ideas count and where you can thrive in a diverse culture
• Explore a world of opportunities for your personal and professional development