Hardware / Software System Performance Expert

Synopsys, Inc.; München; Vor Ort; EUR 120.000 - 160.000; Vollzeit

Zusammenfassung

Synopsys, Inc. is seeking a Senior Architect for System Design Enablement to advance performance models and architecture exploration across SoC and multi-die systems.

You will build virtual prototypes using C/C++, Python and SystemC, collaborate with cross‑functional teams, publish findings, and help drive reference platforms and AI-assisted workflows.

Qualifikationen

• MS or PhD in Electrical/Computer Engineering or CS.
• 8+ years in system architecture and performance modeling.
• Strong C/C++ and Python for modeling and automation.
• Experience with RTL development and verification.
• Experience with virtual prototyping or design-space exploration.
• Excellent technical communication and publications.

Aufgaben

• Develop architecture exploration methodologies for SoC, multi-die, and chiplet systems.
• Build performance models and virtual prototypes using C/C++, Python, and SystemC.
• Create benchmarks, workloads, and design-space exploration tools for scalable evaluation.
• Collaborate with architecture, IP, software, and verification teams.
• Publish findings and present at conferences; contribute to standards and communities.
• Contribute to reference platforms and demonstrations of Synopsys IP and tools.
• Integrate AI-assisted development workflows into rapid prototyping and tooling.

Kenntnisse

C/C++

Python

SystemC

Performance modeling

Architecture evaluation

Hardware/software co-design

Verilog/VHDL familiarity

Technical communication

Ausbildung

MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science

Tools

RTL simulators

Virtual prototyping tools

Design-space exploration tools

Jobbeschreibung

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You bring nearly a decade of experience developing performance models and architectural evaluation methodologies that enable critical design decisions before silicon exists. Your work sits at the convergence of hardware design, software optimization, and system-level analysis, and you have developed a disciplined approach to navigating ambiguity when requirements are still being defined, or stakeholders have not yet aligned on the core technical questions.

You are equally capable of writing performance critical C++ models and Python-based automation frameworks for design-space exploration. Your thinking spans multiple abstraction layers: RTL implementation, embedded firmware, application workloads, and system topology. You understand which layer drives the answer for any given architectural question.

Cross-functional collaboration is a strength. You have worked effectively with architecture teams focused on power, performance, and area trade-offs, software teams optimizing for latency and throughput, and verification teams driving coverage metrics.

At Synopsys, you will contribute to methodologies and reference architectures for next-generation semiconductor systems. The frameworks you develop will influence how customers evaluate chiplet interconnects, multi-die performance, and SoC scalability.

What You’ll Be Doing

• Develop architecture exploration methodologies for SoC, multi-die, and chiplet-based systems to support early design trade-off decisions
• Build performance models and virtual prototyping environments using C/C++, Python, and SystemC to characterize next-generation semiconductor architectures
• Create benchmarks, workloads, and design-space exploration tools that enable scalable evaluation of complex hardware/software systems
• Collaborate with architecture, IP, software, and verification teams across Synopsys to define modeling approaches, validation strategies, and proof-of-concept demonstrations
• Drive technical thought leadership by publishing findings, presenting them at conferences, contributing to standards bodies, and sharing best practices internally and externally
• Contribute to reference platforms and technical demonstrations that showcase Synopsys IP, EDA tools, and system-level solutions to customers and partners
• Integrate AI-assisted development workflows into rapid prototyping, automation, and tooling to accelerate methodology development and technical exploration

The Impact You Will Have

• Enable architecture teams to evaluate and optimize multi-die and chiplet-based systems before physical implementation, reducing costly late-stage design changes
• Accelerate time-to-insight for customers by delivering reusable workloads and performance models that become the foundation for their own evaluations
• Shape the technical direction of Synopsys IP and platform roadmaps by providing data-driven performance analysis and architectural trade-off studies
• Reduce verification and bring-up cycles by delivering validated virtual prototyping environments that software and firmware teams can use before silicon availability
• Strengthen Synopsys customer engagements by contributing to technical demonstrations that prove out real-world use cases

What You’ll Need

• MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• 8+ years of hands‑on experience in system architecture, performance modeling, hardware/software co‑design, or semiconductor verification
• Strong proficiency in C/C++ and Python for performance‑critical modeling, algorithm development, automation, and tooling
• Deep experience with hardware design and verification, including RTL development, simulation, debug, and performance characterization of complex SoC or multi‑die systems
• Proven track record of technical communication through publications, conference presentations, patents, or contributions to industry standards and technical communities
• Experience with virtual prototyping, design‑space exploration tools, or simulation frameworks for architecture evaluation
• Experience integrating AI‑assisted development workflows into rapid prototyping, data analysis, or tool development is a strong plus

Who You Are

• You can take a vague architectural question and turn it into a concrete modeling plan with defined assumptions, measurable outputs, and a timeline that actually holds
• You write code that other engineers can pick up six months later without needing you in the room to explain it
• You are comfortable presenting technical findings to a room that includes both deep RTL experts and software architects who have never touched Verilog, and you calibrate your message accordingly
• You treat proof‑of‑concept work as a forcing function for clarity, not a shortcut, and you know when to stop refining and start sharing results
• You stay current with emerging architectures, chiplet standards, and system‑level design trends, and you bring that perspective into the work without waiting to be asked

The Team You’ll Be Part Of

The System Design Enablement team develops performance models, virtual prototypes, methodologies, and proof‑of‑concept solutions for next‑generation semiconductor systems. Working across hardware, software, and system architecture, the team enables early architecture exploration and system‑level decision making for compute‑intensive applications in areas such as automotive, robotics, and automation. Its work turns emerging requirements into scalable design approaches, reusable assets, and inputs for product roadmaps.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings.