DSP ASIC Verification Engineer - Optical Transmission Systems

Ciena Corporation; Braunschweig; Hybrid; EUR 60.000 - 90.000; Vollzeit

Zusammenfassung

Ciena Corporation in Germany seeks a Digital Design Verification Engineer to validate WaveLogic product family. You will design and execute verification blocks, develop test benches in SystemVerilog UVM, and collaborate with systems engineers to ensure architectural correctness.

The role requires 3+ years of relevant experience, proficiency in SV-UVM and C/C++, and a methodical approach to coverage. You will contribute to verification planning, report progress, and work in a flexible, inclusive

Qualifikationen

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or other applicable scientific discipline.
• 3+ years of experience in digital design verification of complex circuits.
• Experience with SV-UVM, SVA, and C++ in verification environments.
• Creation of verification plans based on functional and architectural specifications.
• Development of verification environments using SV-UVM and C++.
• Application of metric-driven verification methods including functional coverage.
• Experience with EDA verification tools and flows from major vendors.
• Good English communication skills, problem-solving, and ability to work independently.

Aufgaben

• Design and execute verification activities for architectural functional blocks within the WaveLogic product family.
• Analyse architecture and functional requirement specifications and collaborate with systems engineers and architects.
• Develop and implement validation strategies using simulation, formal methods, and coverage techniques.
• Create and integrate verification environments including test benches, agents, scoreboards, and test scenarios using SystemVerilog UVM and/or C.
• Define and implement functional coverage models and contribute to verification planning.
• Perform coverage-driven verification, analyse regression results, and debug failures in collaboration with design engineers.
• Report verification progress, issues, and status updates on a regular basis.

Kenntnisse

SV-UVM

SVA

C++ (verification)

SystemVerilog

English communication

Ausbildung

Master’s degree in Electrical/Computer Engineering or CS

Tools

GIT

Jira

Python

Make

Bash

C

C++

Jobbeschreibung

As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity—driving our business priorities alongside meaningful social, community, and societal impact. Ciena’s WaveLogic family of products is a core component of optical transmission solutions, enabling high-performance telecommunications networks globally. This role contributes to the validation and quality of these products through rigorous digital verification. The position plays a critical role in ensuring reliable functionality across complex subsystems and architectural components.

How you will make an impact:

• Design and execute verification activities for architectural functional blocks within the WaveLogic product family
• Analyse architecture and functional requirement specifications and collaborate with systems engineers and architects
• Develop and implement validation strategies using simulation, formal methods, and coverage techniques
• Create and integrate verification environments including test benches, agents, scoreboards, and test scenarios using SystemVerilog UVM and/or C
• Define and implement functional coverage models and contribute to verification planning
• Perform coverage-driven verification, analyse regression results, and debug failures in collaboration with design engineers
• Report verification progress, issues, and status updates on a regular basis

The must haves:

• Education: Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or other applicable scientific discipline
• Experience: 3+ years of experience in digital design verification of complex circuits
• Application of SV-UVM, SVA, and C++ in verification environments
• Creation of verification plans based on functional and architectural specifications
• Development of verification environments using SV-UVM and C++
• Application of metric-driven verification methods including functional coverage
• Utilization of EDA verification tools and flows from major vendors
• Candidates should have good English communication skills, solid problem-solving capabilities, and demonstrate a high level of motivation with the ability to work independently

Nice to haves:

• Experience: Experience with formal verification methods
• Experience: Experience with coherent DSP architectures
• Experience: Experience with standards and protocols such as OTN/FlexO/B100G and Ethernet (100GE+)
• Experience: Experience using GIT for source code management and revision tracking
• Experience: Experience using Jira for schedule planning, assignment tracking, and bug reporting
• Application of programming languages such as Python, Make, Bash, C, and C++
• Basic communication skills in German

Ciena values the diversity of its workforce and respects its employees as individuals.

We do not tolerate any form of discrimination.

Ciena is an Equal Opportunity Employer, including disability and protected veteran status.

If contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.

#LI-MP2