Design Verification Engineer for Cellular Baseband (m/f/d) #200690368

Apple Technology Engineering B.V. & Co. KG; München; On-site; EUR 90,000 - 130,000; Full time

Job summary

Apple in Munich is seeking a Design Verification Engineer to drive verification of next‑generation baseband IP and SOC components. You will craft reusable UVM environments, develop coverage-driven tests, and collaborate with multi‑functional teams to ensure tape-out readiness.

You will apply ML-driven workflows, improve verification methodologies, and contribute to ML-based tooling to raise efficiency and quality.

Qualifications

• Knowledge of SystemVerilog and UVM.
• Experience with SystemC, C/C++, Python/Perl.
• Ability to develop DV methodologies and test plans.
• Familiarity with LLMs and MCPs in verification.
• Python-based automation skills and data-driven workflows.
• Understanding of constraint random testing and SVA.
• Strong test planning and problem-solving skills.

Responsibilities

• Construct detailed test plans for various components of the design with multi-functional teams.
• Create coverage-driven verification plans from specifications and refine to targets.
• Architect UVM-based, reusable test benches with stimulus, checkers, VIPs, and reference models.
• Leverage ML tools to enhance verification processes for efficiency and quality.
• Design and implement ML-driven workflows to boost team productivity.
• Execute test plans from RTL bring-up to sign-off; report and debug failures.
• Maintain regressions and report progress against plans and coverage metrics.

Skills

SystemVerilog

UVM

SystemC

C/C++

Python

Perl

DV Methodologies

Test planning

LLMs in verification

Education

BSc/MSc in EE/CS/Embedded Eng

Tools

SystemVerilog

UVM

SystemC

Python

Verilog

RTL simulation

Job description

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something.

Description

As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems. Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll develop comprehensive coverage-driven and directed test cases that thoroughly validate complex IP and subsystem designs, working closely with multi-functional teams throughout the process.

In this role, you'll drive methodology innovation by deploying sophisticated tools and techniques that elevate verification practices and ensure tape-out readiness. Collaborating with product development teams across Apple, you'll help deliver cellular systems that redefine industry capabilities and enhance customer experiences globally. This position offers exceptional opportunities to deepen your expertise across cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and sophisticated debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures.

We're looking for experienced engineers with hands-on ASIC design verification experience using reusable verification methodologies such as UVM. The ideal candidate excels at detailed test planning, adapts well to evolving requirements, knows the latest ML-based tools to improve productivity, and is driven to meet the highest quality standards. You thrive in collaborative environments and are eager to tackle the verification challenges of complex, high-performance cellular systems. If you want to contribute to products that impact customers worldwide while advancing your technical expertise, we'd love to hear from you.

Responsibilities

• Construct detailed test plans for various components of the design including use cases, through collaborative work with multi-functional teams.
• Create coverage-driven verification plans from specifications; review and refine to achieve coverage targets.
• Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs, and reference models.
• Leverage Large Language Models (LLMs) to enhance verification processes, delivering improvements in efficiency and quality.
• Design and implement ML-driven workflows that increase team productivity and overall quality of verification.
• Implement test plans from RTL simulation bring-up to sign-off; report and debug failures.
• Maintain regressions and report the verification progress against test plans and coverage metrics.

Minimum Qualifications

• Knowledge of SystemVerilog and UVM.
• Experience with SystemC, C/C++, Python/perl.
• Ability to develop and establish DV Methodologies.
• Ability to use LLMs and MCPs.
• Ability to develop Python-based automation solutions.
• Understanding of constraint random testing, SVA, Coverage driven verification.
• Test planning and problem-solving skills.

Preferred Qualifications

• BSc, MSc, or higher degree in Electrical Engineering/Computer Science, Embedded Engineering or similar
• Experience in C/C++ modeling for design verification.
• Knowledge of 4G/5G cellular physical layer operation (3GPP).
• Experience with verification of embedded processor cores.
• Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
• Knowledge of using LLMs to improve efficiency and quality of verification.
• Understanding of prompt engineering and LLM workflow optimization.