Design Verification Engineer for Cellular Baseband (m/f/d)

Apple; München; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

Apple seeks a Design Verification Engineer in Munich to drive verification for next-gen baseband modems and RF controllers within our silicon group. You will design reusable UVM environments, craft coverage-driven tests, and collaborate across multifunction teams to ensure tape-out readiness.

The role emphasizes hands-on SystemVerilog/UVM expertise, SystemC and C/C++, Python automation, and the use of ML-assisted verification to boost productivity.

Qualifikationen

• Knowledge of SystemVerilog and UVM in industrial DV projects.
• Experience with SystemC, C/C++, Python or Perl for verification tasks.
• Ability to develop DV methodologies and reuse components.
• Experience using LLMs and automated verification tooling.
• Python-based automation skills for verification workflows.
• Familiarity with constraint random testing, SVA and coverage-driven verification.
• Strong test planning and problem-solving abilities.

Aufgaben

• Construct detailed verification plans for design components with multi-functional teams.
• Create coverage-driven verification plans from specifications and refine them.
• Architect UVM-based test benches with stimuli, checkers, VIPs and models.
• Leverage LLMs to enhance verification processes and productivity.
• Design ML-driven workflows to improve verification quality and speed.
• Implement test plans from RTL bring-up to sign-off; debug failures.
• Maintain regressions and report progress against test plans and coverage.

Kenntnisse

SystemVerilog & UVM

SystemC & C/C++

Python scripting

DV methodologies

LLMs MCPs

Constraint random testing

SVA

Test planning

Ausbildung

BSc, MSc or higher in Electrical Engineering/CS/Embedded Eng

Tools

UVM test benches

SystemC modeling

Embedded processor cores verification

Bus Fabric/NOC/AHB/AXI verification

LLM-assisted verification tooling

Jobbeschreibung

Summary

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other’s ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It’s the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you’ll do more than join something — you’ll add something.

Description

As a Design Verification Engineer, you'll be at the center of our silicon design group's verification efforts, ensuring the quality and reliability of next-generation cellular systems. Working on innovative baseband modems and RF link controllers for Apple's SOCs, you'll craft highly reusable UVM verification environments that set the standard for quality and efficiency. You'll develop comprehensive coverage-driven and directed test cases that thoroughly validate complex IP and subsystem designs, working closely with multi-functional teams throughout the process.

In this role, you'll drive methodology innovation by deploying sophisticated tools and techniques that elevate verification practices and ensure tape-out readiness. Collaborating with product development teams across Apple, you'll help deliver cellular systems that redefine industry capabilities and enhance customer experiences globally. This position offers exceptional opportunities to deepen your expertise across cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and sophisticated debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures.

We're looking for engineers with hands-on ASIC design verification experience using reusable verification methodologies such as UVM. The ideal candidate excels at detailed test planning, adapts optimally to evolving requirements, has knowledge of the latest ML-based tools to improve productivity, and is driven to achieve the highest quality standards. You thrive in collaborative environments and are eager to address the verification challenges inherent in complex, high-performance cellular systems. If you want to contribute to products that impact customers worldwide while advancing your technical expertise, we'd love to hear from you.

Responsibilities

• Construct detailed test plans for various components of the design including use cases, through collaborative work with multi-functional teams.
• Create coverage driven verification plans from specifications, review and refine to achieve coverage targets.
• Architect UVM-based, reusable test benches with components for stimulus, checkers, VIPs and reference models.
• Leverage Large Language Models (LLMs) to enhance verification processes, delivering improvements in efficiency and quality.
• Design and implement ML-driven workflows that increase team productivity and overall quality of verification.
• Implement test plans from RTL simulation bring-up to sign-off; report and debug failures.
• Maintain regressions and report the verification progress against test plans and coverage metrics.

Minimum Qualifications

• Knowledge of System Verilog and UVM.
• Experience with System C, C/C++, Python/perl.
• Ability to develop and establish DV Methodologies.
• Ability to use LLMs and MCPs.
• Ability to develop Python-based automation solutions.
• Understanding of constraint random testing, SVA, Coverage driven verification.
• Test planning and problem-solving skills.

Preferred Qualifications

• BSc, MSc. or higher degree in Electrical Engineering/Computer Science, Embedded Engineering or similar
• Experience in C/C++ modeling for design verification.
• Knowledge of 4G/5G cellular physical layer operation (3GPP).
• Experience with verification of embedded processor cores.
• Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
• Knowledge of using LLMs to improve efficiency and quality of verification.
• Understanding of prompt engineering and LLM workflow optimization.

At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple’s workplace

Role Number: 200679163-1731