Design Verification Engineer (Digital Design) (m/f/x)

Last Mile Semiconductor GmbH; Dresden; Hybrid; EUR 85.000 - 110.000; Vollzeit

Benefits dieser Stelle

Creative freedom

Hybrid work

Gym access

Pension plan

Job ticket

Zusammenfassung

Last Mile Semiconductor GmbH in Dresden seeks an experienced Design Verification professional to join our digital design team. You will develop verification plans, test benches, and automated tests for digital blocks, subsystems, and SoC integrations from requirements through RTL and netlist verification.

You will help verify interactions between digital logic and analog/RF or mixed-signal blocks, and collaborate with design, firmware, and system engineers to ensure robust validation.

Qualifikationen

• Bachelor's or Master's degree in electrical engineering, telecommunications engineering, microelectronics, computer engineering, computer science, or a comparable qualification.
• Several years of practical experience in digital design verification, ASIC/SoC verification, FPGA verification, or a comparable hardware verification field; typically at least five years of relevant professional experience.
• Strong understanding of digital design fundamentals: synchronous logic, FSMs, registers, memory, interfaces, timing, clocking, reset behavior.

Aufgaben

• Developing and maintaining verification plans based on use cases, requirements and specs in collaboration with design, firmware and system teams.
• Translating requirements into test scenarios, corner cases, assertions, checkers and coverage targets.
• Design and implement simulation-based verification environments for RTL and mixed-signal interfaces.
• Develop directed tests, constrained random tests and regression tests using SystemVerilog, Python, cocotb and C.
• Verify RTL, netlists, and perform pre-tape-out netlist/SDF verification; support post-silicon validation if needed.
• Maintain automated regression flows, CI-based test execution and reporting.
• Analyze results, waveforms, logs, and defects; document findings with technical evidence.
• Collaborate with cross-functional teams and improve verification methods and documentation.

Kenntnisse

SystemVerilog

Python

C++

C

Cocotb

RTL verification

Debugging

English

Ausbildung

Bachelor's or Master's in Electrical Engineering

Tools

Cocotb

ModelSim/QuestaSim

Git

Jobbeschreibung

This job description is available in the following languages:

We are looking for an experienced Design Verification professional to join our digital design team and work with us on the development of modern ASIC and SoC systems. In this role, you will develop and maintain verification plans, test benches, and automated tests for digital design blocks, subsystems, and SoC integrations-from requirements analysis through RTL and netlist verification to support during validation.

If you systematically analyze digital designs, methodically narrow down complex fault scenarios, and enjoy working at the intersection of digital design, analog/RF, firmware, and system engineering, you’ve come to the right place. A particular focus of this position is on verifying the interaction between digital logic and analog/RF or mixed-signal blocks. At the same time, the role is also of interest to experienced verification engineers without in-depth mixed-signal experience.

Your Responsibilities:

• Developing and maintaining verification plans based on use cases, functional requirements, and technical specifications in close collaboration with Digital Design, Analog/RF Design, Firmware, and System Engineering.
• Translating system, architecture, and block requirements into test scenarios, corner cases, assertions, checkers, and coverage targets.
• Reviewing specifications for completeness, consistency, clarity, and verifiability, as well as identifying missing requirements and undefined edge cases.
• Design and implementation of simulation-based verification environments for RTL as well as for digital and mixed-signal interfaces.
• Development of directed tests, constrained random tests, and regression tests using SystemVerilog, Python, cocotb, and C.
• Verification at the block and top-level in simulation and on FPGAs, as well as performing pre-tape-out netlist and SDF verification.
• Support for the verification of a multicore system based on the RISC-V architecture, including low- and high-speed peripherals, security functions, clock-domain crossings, power management, and low-power consumption requirements.
• Verification of the interaction between digital logic and analog/RF or mixed-signal blocks using appropriate behavioral models, particularly with regard to data formats, sampling relationships, quantization, saturation, latencies, and calibration procedures.
• Analysis of simulation results, waveforms, logs, assertions, transactions, and test data, as well as systematic identification of the causes of errors in the design, testbench, model, specification, or test environment.
• Documentation, technical evaluation, and tracking of defects in close collaboration with the digital design team.
• Analysis, improvement, and reporting of functional coverage and code coverage.
• Verification of RTL and netlists, as well as support for post-silicon validation, if required by the respective project.
• Maintenance of automated regression flows, CI-based test execution, and the associated reporting.
• Maintaining verification plans, test specifications, regression results, coverage reports, and defect documentation.
• Continuous improvement of verification methods, reusable components, review practices, and documentation standards.

Your Profile:

• A bachelor’s or master’s degree in electrical engineering, telecommunications engineering, microelectronics, computer engineering, computer science, or a comparable qualification.
• Several years of practical experience in digital design verification, ASIC/SoC verification, FPGA verification, or a comparable hardware verification field; typically, you have at least five years of relevant professional experience.
• A solid understanding of digital design fundamentals, particularly synchronous logic, finite-state machines, registers, memory, interfaces, timing, clocking, and reset behavior.
• Practical experience with SystemVerilog or a comparable hardware verification language.
• Experience in developing and maintaining verification plans, as well as in deriving test scenarios, corner cases, and acceptance criteria from technical specifications.
• Excellent methodical debugging skills in analyzing waveforms, logs, assertions, transactions, and test results.
• Experience with Python and cocotb, and ideally with C for test development, reference models, or test automation.
• You can systematically reproduce technical errors, narrow down their causes, and document the results with clear technical evidence.
• A structured, analytical, and solution-oriented approach to work, as well as a high degree of initiative and personal responsibility.
• You enjoy working closely with digital design, analog/RF design, firmware, and system engineering teams and can communicate technical matters clearly and precisely.
• Good written and spoken English skills for working in an international team.

Nice-to-have:

• Experience with the verification of mixed-signal or RF interfaces, particularly ADC/DAC data paths, PLL control, clock generation, calibration, AGC, or RF control paths.
• Experience with behavioral modeling, such as SystemVerilog Real Number Modeling, Verilog-AMS, SystemC, MATLAB/Simulink, or comparable approaches.
• Experience with
  • assertions, functional coverage, code coverage, linting, CDC/RDC analysis, formal verification, or equivalence checking.
  • ASIC design flows, FPGA prototyping, emulation, tape-out preparation, or silicon bring-up.
  • UPF verification and low-power design.
  • Fixed-point data paths, quantization, saturation, dynamic range, and numerical reference models.
  • the definition or verification of hardware/software interfaces, register maps, and behavior visible to firmware.
  • Simulators, waveform viewers, version control, issue trackers, CI systems, and automated regression infrastructure.
• Knowledge of Tcl, Perl, C++, or other scripting and programming languages for test automation and regression analysis.

We offer:

Creative freedom & responsibility

• Ample creative freedom and genuine ownership instead of micromanagement
• Short decision-making paths and direct influence on strategic decisions
• A tangible contribution to the success of our product and company
• The opportunity to play a key role in a growing deep-tech company
• Contributing to a technology that can transform the future of wireless communication
• Employer contribution toward the Deutschlandticket or DVB Jobticket in the amount of €55.10 per month
• Alternatively, an employer contribution toward the JobRad in the amount of €54.90 per month
• Unlimited free gym access right in the building
• Retirement plan and disability insurance with contributions ranging from €100 to €200 per month

Flexibility & Work Environment

• Flexible work hours with core hours from 10:00 a.m. to 3:00 p.m.
• Hybrid work with a high degree of flexibility
• Modern hardware and professional work equipment
• Bright, modern office spaces in a central location in Dresden
• Ergonomically designed workstations

Team & Culture

• An international team with flat hierarchies and short lines of communication
• Direct interaction with management and technical decision-makers
• Colleagues who support one another and share knowledge
• Lunch breaks together and regular team events
• A corporate culture in which initiative and new ideas are expressly encouraged

Employee Benefits

Flexible working hours High-quality technical equipment employee discounts through corporate benefits Personal feedback and development conversations Bikeleasing Diverse part-time options Shower facilities daycare support Start-up spirit free gym Free parking Offer sports courses on site Job ticket Subsidies for public transportation Employee referral bonus Daycare subsidy Team events home office option Individual training program 30 days of annual leave Personal feedback and development discussions Pension plan Flexible working hours Ergonomic workplaces Fitness studio Good public transportation connections Bicycle leasing (Jobrad) Company pension scheme

Locations

The position 'Design Verification Engineer (Digital Design) (m/f/x)' is available for the following locations: Bamberger Strasse 1, 01187 Dresden.

Keywords

ASIC Microelectronics DECT NR+ Engineer Dresden SoC System on Chip Chip Design System Wireless NRplus OFDM