Cellular SoC Frontend STA Engineer (m/f/d)

Omaze; München; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

Apple in Munich seeks a Frontend-STA engineer to develop timing constraints for synthesis, P&R and sign-off STA. You will link digital and physical design, optimize clock structures, power, performance and area, and improve flows with CAD/PD teams.

You will collaborate with RTL designers and PD teams, using PrimeTime/Tempus for multi-mode/multi-corner analysis, and bring strong Verilog expertise to ensure sign-off quality.

Qualifikationen

• Hands-on experience on multiple projects with constraint development, analysis, and debugging.
• Proven experience with industry-standard STA tools such as PrimeTime or Tempus and multi-mode/multi-corner analysis.
• Understanding of hierarchical design, timing budgeting, asynchronous interfaces, DFT, and timing/physical convergence.
• Proficient in TCL, Python, Shell scripting, Linux, and revision control (e.g., Perforce).
• Strong Verilog knowledge with ability to analyze RTL/Netlist designs.
• Good communication skills and ability to collaborate between RTL-Design and Physical-Design teams.
• English proficiency required.

Aufgaben

• Develop and deliver timing constraints for synthesis, P&R, and sign-off STA.
• Work on partition- and SoC-level constraints and verify results post-synthesis for all STA modes.
• Act as liaison between digital and physical design; ensure sign-off quality of timing constraints.
• Collaborate with digital designers to understand clock structures and optimize power, performance and area.
• Improve development flows with CAD and PD teams.

Kenntnisse

Constraint development

STA tools

Verilog analysis

Scripting (Python/TCL)

English proficiency

Ausbildung

Bachelor's or Master's in EE/CS

PhD in a relevant field (optional)

Tools

PrimeTime

Tempus

Jobbeschreibung

Summary

Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, amazing people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

In this role, you will be a key part of the Cellular SoC Integration team in Munich, Germany. As Frontend-STA engineer you are the focal point for constraints development as well as design- and timing analysis. Together with RTL designers, Physical designers, and other integration teams, you will work on very exciting designs and sophisticated technology nodes.

Description

You will be responsible for constraint development, including deliveries for synthesis, PnR, and sign-off STA. You will work on partition- as well as SoC-level and verify the results post-synthesis for all STA modes.

In this role, you will be the link between digital design, mixed-signal design (.lib definition), and physical design. Your responsibility is to achieve sign-off quality of timing constraints, based on stakeholder requirements.

Further, you will closely collaborate with digital designers to understand the design intent and its clock structure to optimize power, performance, and area. With CAD and PD teams you will continuously improve development flows.

Minimum Qualifications

• Hands-on experience on multiple projects with constraint development, analysis, and debugging.
• Proven experience with industry-standard tools for STA, e.g., PrimeTime or Tempus, including multi-mode multi-corner analysis.
• Understanding of hierarchical design approaches, timing budgeting, asynchronous interfaces, DFT implementations, as well as timing and physical convergence.
• Proficient in day-to-day usage of scripting languages (TCL, Perl, Shell, Bash, Python), Linux, and revision control systems (e.g., PerForce).
• Strong understanding of Verilog with the ability to analyse RTL/Netlist designs.
• Strong interpersonal and communication skills, as well as the ability to find effective technical solutions between RTL-Design and Physical-Design teams.
• English language proficiency is required for this position.

Preferred Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Science/Software Engineering, or equivalent with 5+ years of working experience, or a PhD in a relevant field with 3+ years of proven experience.
• A strong background in RTL design and SoC practices, such as multiple voltage and clock domains, integration of mixed-signal IPs, and power optimizations, is highly valued.
• Experience with synthesis flows and optimization techniques for power, performance, and area trade-offs, as well as logic equivalence checking or ECO implementation, is a plus.
• Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.

At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced, and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. We will work with applicants to make any reasonable accommodations.

At Apple, we believe accessibility is a fundamental human right. You'll find that idea reflected in everything here - in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about accessibility in Apple's workplace

Role Number: 200633022-1731