ASIC Analog Layout Engineer (m/f/d)

AUMOVIO SE Haupverwaltung; Deutschland; Vor Ort; EUR 75.000 - 105.000; Vollzeit

Zusammenfassung

AUMOVIO SE Haupverwaltung is seeking an experienced ASIC Layout Engineer (m/f/d) to drive the top-level integration of analog and mixed-signal ICs. You will ensure robust, DRC-compliant layouts with optimal area utilization and collaborate closely with analog circuit designers and other layout engineers.

In this role you will define the top-level floorplan, padframe design and bonding diagrams in coordination with other domains and coordinate with fellow layouters to drive floorplans according

Aufgaben

• Top-level layout integration of analog/mixed-signal chips (analog on top)
• Defining top-level floorplan, padframe design and bonding diagrams in coordination with other domains
• Coordinating with other layouters and drive floorplans according to the chip top level

Jobbeschreibung

Company Description

At AUMOVIO, we own what we do: Developing and producing hardware, software, and services that shape the future of mobility. But what truly sets us apart are our people. People who thrive in our winning culture, driven by bold ideas. People who take a leap and create meaningful difference- together. Because we believe that the future belongs to those who own it. That's why we foster a culture where you own every step of the way. Own your career, your growth, your skills, and your impact. Join us and own what's next.

Job Description

As an ASIC Layout Engineer (m/f/d), you will be responsible for the top-level integration of analog and mixed-signal ICs. You will drive the layout development process, ensuring robust, DRC-compliant designs with optimal area utilization. You will collaborate closely with analog circuit designers and other layout engineers to deliver high-quality silicon.

Key Responsibilities

• Responsibility for top-level layout integration of analog/mixed-signal chips (analog on top)
• Defining toplevel floorplan, padframe design and bonding diagrams in coordination with other domains
• Coordinating with other layouters and drive floorplans according to the chip top level* (trim?)